1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 80 unchanged lines hidden (view full) --- 89 MsrRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 90 IntRegIndex _op1, uint8_t _byteMask) : 91 MsrBase(mnem, _machInst, __opClass, _byteMask), op1(_op1) 92 {} 93 94 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 95}; 96 |
97class ImmOp : public PredOp 98{ 99 protected: 100 uint32_t imm; 101 102 ImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 103 uint32_t _imm) : 104 PredOp(mnem, _machInst, __opClass), imm(_imm) 105 {} 106 107 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 108}; 109 |
110class RegRegOp : public PredOp 111{ 112 protected: 113 IntRegIndex dest; 114 IntRegIndex op1; 115 116 RegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 117 IntRegIndex _dest, IntRegIndex _op1) : --- 113 unchanged lines hidden --- |