1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 80 unchanged lines hidden (view full) --- 89 MsrRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 90 IntRegIndex _op1, uint8_t _byteMask) : 91 MsrBase(mnem, _machInst, __opClass, _byteMask), op1(_op1) 92 {} 93 94 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 95}; 96 |
97class RegRegOp : public PredOp |
98{ 99 protected: 100 IntRegIndex dest; 101 IntRegIndex op1; 102 |
103 RegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 104 IntRegIndex _dest, IntRegIndex _op1) : |
105 PredOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1) 106 {} 107 108 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 109}; 110 111class RegImmRegOp : public PredOp 112{ --- 105 unchanged lines hidden --- |