1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 128 unchanged lines hidden (view full) --- 137 uint32_t _imm) : 138 PredOp(mnem, _machInst, __opClass), 139 dest(_dest), op1(_op1), op2(_op2), imm(_imm) 140 {} 141 142 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 143}; 144 |
145class RegRegRegRegOp : public PredOp 146{ 147 protected: 148 IntRegIndex dest; 149 IntRegIndex op1; 150 IntRegIndex op2; 151 IntRegIndex op3; 152 153 RegRegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 154 IntRegIndex _dest, IntRegIndex _op1, 155 IntRegIndex _op2, IntRegIndex _op3) : 156 PredOp(mnem, _machInst, __opClass), 157 dest(_dest), op1(_op1), op2(_op2), op3(_op3) 158 {} 159 160 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 161}; 162 |
163class RegRegRegOp : public PredOp 164{ 165 protected: 166 IntRegIndex dest; 167 IntRegIndex op1; 168 IntRegIndex op2; 169 170 RegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, --- 29 unchanged lines hidden --- |