1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 128 unchanged lines hidden (view full) --- 137 uint32_t _imm) : 138 PredOp(mnem, _machInst, __opClass), 139 dest(_dest), op1(_op1), op2(_op2), imm(_imm) 140 {} 141 142 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 143}; 144 |
145class RegRegRegOp : public PredOp 146{ 147 protected: 148 IntRegIndex dest; 149 IntRegIndex op1; 150 IntRegIndex op2; 151 152 RegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 153 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) : 154 PredOp(mnem, _machInst, __opClass), 155 dest(_dest), op1(_op1), op2(_op2) 156 {} 157 158 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 159}; 160 |
161class RegImmRegShiftOp : public PredOp 162{ 163 protected: 164 IntRegIndex dest; 165 uint32_t imm; 166 IntRegIndex op1; 167 int32_t shiftAmt; 168 ArmShiftType shiftType; --- 13 unchanged lines hidden --- |