mem64.hh (14150:1391e94a7b95) mem64.hh (14240:5b9499c2ae14)
1/*
2 * Copyright (c) 2011-2013,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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44
45namespace ArmISA
46{
47
48class SysDC64 : public MiscRegOp64
49{
50 protected:
51 IntRegIndex base;
1/*
2 * Copyright (c) 2011-2013,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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44
45namespace ArmISA
46{
47
48class SysDC64 : public MiscRegOp64
49{
50 protected:
51 IntRegIndex base;
52 IntRegIndex dest;
52 MiscRegIndex dest;
53 uint64_t imm;
54
55 SysDC64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
53 uint64_t imm;
54
55 SysDC64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
56 IntRegIndex _base, MiscRegIndex miscReg, uint64_t _imm)
56 IntRegIndex _base, MiscRegIndex _dest, uint64_t _imm)
57 : MiscRegOp64(mnem, _machInst, __opClass, false),
57 : MiscRegOp64(mnem, _machInst, __opClass, false),
58 base(_base), dest((IntRegIndex)miscReg), imm(_imm)
58 base(_base), dest(_dest), imm(_imm)
59 {}
60
61 std::string generateDisassembly(
62 Addr pc, const SymbolTable *symtab) const override;
63};
64
65class MightBeMicro64 : public ArmStaticInst
66{

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60
61 std::string generateDisassembly(
62 Addr pc, const SymbolTable *symtab) const override;
63};
64
65class MightBeMicro64 : public ArmStaticInst
66{

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