1/* 2 * Copyright (c) 2011-2013,2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 42 unchanged lines hidden (view full) --- 51 IntRegIndex dest; 52 uint64_t imm; 53 54 SysDC64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 55 IntRegIndex _base, MiscRegIndex miscReg, uint64_t _imm) 56 : ArmStaticInst(mnem, _machInst, __opClass), base(_base), 57 dest((IntRegIndex)miscReg), imm(_imm) 58 {} |
59 std::string generateDisassembly( 60 Addr pc, const SymbolTable *symtab) const override; |
61}; 62 63class MightBeMicro64 : public ArmStaticInst 64{ 65 protected: 66 MightBeMicro64(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 67 : ArmStaticInst(mnem, _machInst, __opClass) 68 {} --- 40 unchanged lines hidden (view full) --- 109 110 virtual 111 ~Memory64() 112 { 113 delete [] uops; 114 } 115 116 StaticInstPtr |
117 fetchMicroop(MicroPC microPC) const override |
118 { 119 assert(uops != NULL && microPC < numMicroops); 120 return uops[microPC]; 121 } 122 123 void startDisassembly(std::ostream &os) const; 124 125 unsigned memAccessFlags; --- 6 unchanged lines hidden (view full) --- 132 protected: 133 int64_t imm; 134 135 MemoryImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 136 IntRegIndex _dest, IntRegIndex _base, int64_t _imm) 137 : Memory64(mnem, _machInst, __opClass, _dest, _base), imm(_imm) 138 {} 139 |
140 std::string generateDisassembly( 141 Addr pc, const SymbolTable *symtab) const override; |
142}; 143 144class MemoryDImm64 : public MemoryImm64 145{ 146 protected: 147 IntRegIndex dest2; 148 149 MemoryDImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 150 IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, 151 int64_t _imm) 152 : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm), 153 dest2(_dest2) 154 {} 155 |
156 std::string generateDisassembly( 157 Addr pc, const SymbolTable *symtab) const override; |
158}; 159 160class MemoryDImmEx64 : public MemoryDImm64 161{ 162 protected: 163 IntRegIndex result; 164 165 MemoryDImmEx64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 166 IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2, 167 IntRegIndex _base, int32_t _imm) 168 : MemoryDImm64(mnem, _machInst, __opClass, _dest, _dest2, 169 _base, _imm), result(_result) 170 {} 171 |
172 std::string generateDisassembly( 173 Addr pc, const SymbolTable *symtab) const override; |
174}; 175 176class MemoryPreIndex64 : public MemoryImm64 177{ 178 protected: 179 MemoryPreIndex64(const char *mnem, ExtMachInst _machInst, 180 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 181 int64_t _imm) 182 : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm) 183 {} 184 |
185 std::string generateDisassembly( 186 Addr pc, const SymbolTable *symtab) const override; |
187}; 188 189class MemoryPostIndex64 : public MemoryImm64 190{ 191 protected: 192 MemoryPostIndex64(const char *mnem, ExtMachInst _machInst, 193 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 194 int64_t _imm) 195 : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm) 196 {} 197 |
198 std::string generateDisassembly( 199 Addr pc, const SymbolTable *symtab) const override; |
200}; 201 202class MemoryReg64 : public Memory64 203{ 204 protected: 205 IntRegIndex offset; 206 ArmExtendType type; 207 uint64_t shiftAmt; 208 209 MemoryReg64(const char *mnem, ExtMachInst _machInst, 210 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 211 IntRegIndex _offset, ArmExtendType _type, 212 uint64_t _shiftAmt) 213 : Memory64(mnem, _machInst, __opClass, _dest, _base), 214 offset(_offset), type(_type), shiftAmt(_shiftAmt) 215 {} 216 |
217 std::string generateDisassembly( 218 Addr pc, const SymbolTable *symtab) const override; |
219}; 220 221class MemoryRaw64 : public Memory64 222{ 223 protected: 224 MemoryRaw64(const char *mnem, ExtMachInst _machInst, 225 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base) 226 : Memory64(mnem, _machInst, __opClass, _dest, _base) 227 {} 228 |
229 std::string generateDisassembly( 230 Addr pc, const SymbolTable *symtab) const override; |
231}; 232 233class MemoryEx64 : public Memory64 234{ 235 protected: 236 IntRegIndex result; 237 238 MemoryEx64(const char *mnem, ExtMachInst _machInst, 239 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 240 IntRegIndex _result) 241 : Memory64(mnem, _machInst, __opClass, _dest, _base), result(_result) 242 {} 243 |
244 std::string generateDisassembly( 245 Addr pc, const SymbolTable *symtab) const override; |
246}; 247 248class MemoryLiteral64 : public Memory64 249{ 250 protected: 251 int64_t imm; 252 253 MemoryLiteral64(const char *mnem, ExtMachInst _machInst, 254 OpClass __opClass, IntRegIndex _dest, int64_t _imm) 255 : Memory64(mnem, _machInst, __opClass, _dest, INTREG_ZERO), imm(_imm) 256 {} 257 |
258 std::string generateDisassembly( 259 Addr pc, const SymbolTable *symtab) const override; |
260}; 261} 262 263#endif //__ARCH_ARM_INSTS_MEM_HH__ |