mem.hh (7428:eea9a618c882) mem.hh (7646:a444dbee8c07)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 63 unchanged lines hidden (view full) ---

72 DecrementBefore,
73 IncrementAfter,
74 IncrementBefore
75 };
76 protected:
77 IntRegIndex base;
78 AddrMode mode;
79 bool wb;
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 63 unchanged lines hidden (view full) ---

72 DecrementBefore,
73 IncrementAfter,
74 IncrementBefore
75 };
76 protected:
77 IntRegIndex base;
78 AddrMode mode;
79 bool wb;
80 static const unsigned numMicroops = 2;
80
81
82 StaticInstPtr *uops;
83
81 RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
82 IntRegIndex _base, AddrMode _mode, bool _wb)
83 : PredOp(mnem, _machInst, __opClass),
84 RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
85 IntRegIndex _base, AddrMode _mode, bool _wb)
86 : PredOp(mnem, _machInst, __opClass),
84 base(_base), mode(_mode), wb(_wb)
87 base(_base), mode(_mode), wb(_wb), uops(NULL)
85 {}
86
88 {}
89
90 virtual
91 ~RfeOp()
92 {
93 delete uops;
94 }
95
96 StaticInstPtr
97 fetchMicroop(MicroPC microPC)
98 {
99 assert(uops != NULL && microPC < numMicroops);
100 return uops[microPC];
101 }
102
87 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
88};
89
90// The address is a base register plus an immediate.
91class SrsOp : public PredOp
92{
93 public:
94 enum AddrMode {
95 DecrementAfter,
96 DecrementBefore,
97 IncrementAfter,
98 IncrementBefore
99 };
100 protected:
101 uint32_t regMode;
102 AddrMode mode;
103 bool wb;
103 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
104};
105
106// The address is a base register plus an immediate.
107class SrsOp : public PredOp
108{
109 public:
110 enum AddrMode {
111 DecrementAfter,
112 DecrementBefore,
113 IncrementAfter,
114 IncrementBefore
115 };
116 protected:
117 uint32_t regMode;
118 AddrMode mode;
119 bool wb;
120 static const unsigned numMicroops = 2;
104
121
122 StaticInstPtr *uops;
123
105 SrsOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
106 uint32_t _regMode, AddrMode _mode, bool _wb)
107 : PredOp(mnem, _machInst, __opClass),
124 SrsOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
125 uint32_t _regMode, AddrMode _mode, bool _wb)
126 : PredOp(mnem, _machInst, __opClass),
108 regMode(_regMode), mode(_mode), wb(_wb)
127 regMode(_regMode), mode(_mode), wb(_wb), uops(NULL)
109 {}
110
128 {}
129
130 virtual
131 ~SrsOp()
132 {
133 delete uops;
134 }
135
136 StaticInstPtr
137 fetchMicroop(MicroPC microPC)
138 {
139 assert(uops != NULL && microPC < numMicroops);
140 return uops[microPC];
141 }
142
111 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
112};
113
114class Memory : public PredOp
115{
116 public:
117 enum AddrMode {
118 AddrMd_Offset,
119 AddrMd_PreIndex,
120 AddrMd_PostIndex
121 };
122
123 protected:
124
125 IntRegIndex dest;
126 IntRegIndex base;
127 bool add;
143 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
144};
145
146class Memory : public PredOp
147{
148 public:
149 enum AddrMode {
150 AddrMd_Offset,
151 AddrMd_PreIndex,
152 AddrMd_PostIndex
153 };
154
155 protected:
156
157 IntRegIndex dest;
158 IntRegIndex base;
159 bool add;
160 static const unsigned numMicroops = 3;
128
161
162 StaticInstPtr *uops;
163
129 Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
130 IntRegIndex _dest, IntRegIndex _base, bool _add)
131 : PredOp(mnem, _machInst, __opClass),
164 Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
165 IntRegIndex _dest, IntRegIndex _base, bool _add)
166 : PredOp(mnem, _machInst, __opClass),
132 dest(_dest), base(_base), add(_add)
167 dest(_dest), base(_base), add(_add), uops(NULL)
133 {}
134
168 {}
169
170 virtual
171 ~Memory()
172 {
173 delete [] uops;
174 }
175
176 StaticInstPtr
177 fetchMicroop(MicroPC microPC)
178 {
179 assert(uops != NULL && microPC < numMicroops);
180 return uops[microPC];
181 }
182
135 virtual void
136 printOffset(std::ostream &os) const
137 {}
138
139 virtual void
140 printDest(std::ostream &os) const
141 {
142 printReg(os, dest);

--- 285 unchanged lines hidden --- 		183 virtual void
184 printOffset(std::ostream &os) const
185 {}
186
187 virtual void
188 printDest(std::ostream &os) const
189 {
190 printReg(os, dest);

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