mem.hh (7131:ab3a70a37ca8) mem.hh (7132:83b433d6e600)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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42#ifndef __ARCH_ARM_MEM_HH__
43#define __ARCH_ARM_MEM_HH__
44
45#include "arch/arm/insts/pred_inst.hh"
46
47namespace ArmISA
48{
49
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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42#ifndef __ARCH_ARM_MEM_HH__
43#define __ARCH_ARM_MEM_HH__
44
45#include "arch/arm/insts/pred_inst.hh"
46
47namespace ArmISA
48{
49
50class MemoryNew : public PredOp
50class Memory : public PredOp
51{
52 public:
53 enum AddrMode {
54 AddrMd_Offset,
55 AddrMd_PreIndex,
56 AddrMd_PostIndex
57 };
58
59 protected:
60
61 IntRegIndex dest;
62 IntRegIndex base;
63 bool add;
64
51{
52 public:
53 enum AddrMode {
54 AddrMd_Offset,
55 AddrMd_PreIndex,
56 AddrMd_PostIndex
57 };
58
59 protected:
60
61 IntRegIndex dest;
62 IntRegIndex base;
63 bool add;
64
65 MemoryNew(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
66 IntRegIndex _dest, IntRegIndex _base, bool _add)
65 Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
66 IntRegIndex _dest, IntRegIndex _base, bool _add)
67 : PredOp(mnem, _machInst, __opClass),
68 dest(_dest), base(_base), add(_add)
69 {}
70
71 virtual void
72 printOffset(std::ostream &os) const
73 {}
74
75 void printInst(std::ostream &os, AddrMode addrMode) const;
76};
77
78// The address is a base register plus an immediate.
67 : PredOp(mnem, _machInst, __opClass),
68 dest(_dest), base(_base), add(_add)
69 {}
70
71 virtual void
72 printOffset(std::ostream &os) const
73 {}
74
75 void printInst(std::ostream &os, AddrMode addrMode) const;
76};
77
78// The address is a base register plus an immediate.
79class MemoryNewImm : public MemoryNew
79class MemoryImm : public Memory
80{
81 protected:
82 int32_t imm;
83
80{
81 protected:
82 int32_t imm;
83
84 MemoryNewImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
85 IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm)
86 : MemoryNew(mnem, _machInst, __opClass, _dest, _base, _add), imm(_imm)
84 MemoryImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
85 IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm)
86 : Memory(mnem, _machInst, __opClass, _dest, _base, _add), imm(_imm)
87 {}
88
89 void
90 printOffset(std::ostream &os) const
91 {
92 int32_t pImm = imm;
93 if (!add)
94 pImm = -pImm;
95 ccprintf(os, "#%d", pImm);
96 }
97};
98
99// The address is a shifted register plus an immediate
87 {}
88
89 void
90 printOffset(std::ostream &os) const
91 {
92 int32_t pImm = imm;
93 if (!add)
94 pImm = -pImm;
95 ccprintf(os, "#%d", pImm);
96 }
97};
98
99// The address is a shifted register plus an immediate
100class MemoryNewReg : public MemoryNew
100class MemoryReg : public Memory
101{
102 protected:
103 int32_t shiftAmt;
104 ArmShiftType shiftType;
105 IntRegIndex index;
106
101{
102 protected:
103 int32_t shiftAmt;
104 ArmShiftType shiftType;
105 IntRegIndex index;
106
107 MemoryNewReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
108 IntRegIndex _dest, IntRegIndex _base, bool _add,
109 int32_t _shiftAmt, ArmShiftType _shiftType,
110 IntRegIndex _index)
111 : MemoryNew(mnem, _machInst, __opClass, _dest, _base, _add),
107 MemoryReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
108 IntRegIndex _dest, IntRegIndex _base, bool _add,
109 int32_t _shiftAmt, ArmShiftType _shiftType,
110 IntRegIndex _index)
111 : Memory(mnem, _machInst, __opClass, _dest, _base, _add),
112 shiftAmt(_shiftAmt), shiftType(_shiftType), index(_index)
113 {}
114
115 void
116 printOffset(std::ostream &os) const
117 {
118 if (!add)
119 os << "-";

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145 }
146 break;
147 }
148 }
149 }
150};
151
152template<class Base>
112 shiftAmt(_shiftAmt), shiftType(_shiftType), index(_index)
113 {}
114
115 void
116 printOffset(std::ostream &os) const
117 {
118 if (!add)
119 os << "-";

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145 }
146 break;
147 }
148 }
149 }
150};
151
152template<class Base>
153class MemoryNewOffset : public Base
153class MemoryOffset : public Base
154{
155 protected:
154{
155 protected:
156 MemoryNewOffset(const char *mnem, ExtMachInst _machInst,
157 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
158 bool _add, int32_t _imm)
156 MemoryOffset(const char *mnem, ExtMachInst _machInst,
157 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
158 bool _add, int32_t _imm)
159 : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
160 {}
161
159 : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
160 {}
161
162 MemoryNewOffset(const char *mnem, ExtMachInst _machInst,
163 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
164 bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
165 IntRegIndex _index)
162 MemoryOffset(const char *mnem, ExtMachInst _machInst,
163 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
164 bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
165 IntRegIndex _index)
166 : Base(mnem, _machInst, __opClass, _dest, _base, _add,
167 _shiftAmt, _shiftType, _index)
168 {}
169
170 std::string
171 generateDisassembly(Addr pc, const SymbolTable *symtab) const
172 {
173 std::stringstream ss;
166 : Base(mnem, _machInst, __opClass, _dest, _base, _add,
167 _shiftAmt, _shiftType, _index)
168 {}
169
170 std::string
171 generateDisassembly(Addr pc, const SymbolTable *symtab) const
172 {
173 std::stringstream ss;
174 this->printInst(ss, MemoryNew::AddrMd_Offset);
174 this->printInst(ss, Memory::AddrMd_Offset);
175 return ss.str();
176 }
177};
178
179template<class Base>
175 return ss.str();
176 }
177};
178
179template<class Base>
180class MemoryNewPreIndex : public Base
180class MemoryPreIndex : public Base
181{
182 protected:
181{
182 protected:
183 MemoryNewPreIndex(const char *mnem, ExtMachInst _machInst,
184 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
185 bool _add, int32_t _imm)
183 MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
184 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
185 bool _add, int32_t _imm)
186 : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
187 {}
188
186 : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
187 {}
188
189 MemoryNewPreIndex(const char *mnem, ExtMachInst _machInst,
190 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
191 bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
192 IntRegIndex _index)
189 MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
190 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
191 bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
192 IntRegIndex _index)
193 : Base(mnem, _machInst, __opClass, _dest, _base, _add,
194 _shiftAmt, _shiftType, _index)
195 {}
196
197 std::string
198 generateDisassembly(Addr pc, const SymbolTable *symtab) const
199 {
200 std::stringstream ss;
193 : Base(mnem, _machInst, __opClass, _dest, _base, _add,
194 _shiftAmt, _shiftType, _index)
195 {}
196
197 std::string
198 generateDisassembly(Addr pc, const SymbolTable *symtab) const
199 {
200 std::stringstream ss;
201 this->printInst(ss, MemoryNew::AddrMd_PreIndex);
201 this->printInst(ss, Memory::AddrMd_PreIndex);
202 return ss.str();
203 }
204};
205
206template<class Base>
202 return ss.str();
203 }
204};
205
206template<class Base>
207class MemoryNewPostIndex : public Base
207class MemoryPostIndex : public Base
208{
209 protected:
208{
209 protected:
210 MemoryNewPostIndex(const char *mnem, ExtMachInst _machInst,
211 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
212 bool _add, int32_t _imm)
210 MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
211 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
212 bool _add, int32_t _imm)
213 : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
214 {}
215
213 : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
214 {}
215
216 MemoryNewPostIndex(const char *mnem, ExtMachInst _machInst,
217 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
218 bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
219 IntRegIndex _index)
216 MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
217 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
218 bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
219 IntRegIndex _index)
220 : Base(mnem, _machInst, __opClass, _dest, _base, _add,
221 _shiftAmt, _shiftType, _index)
222 {}
223
224 std::string
225 generateDisassembly(Addr pc, const SymbolTable *symtab) const
226 {
227 std::stringstream ss;
220 : Base(mnem, _machInst, __opClass, _dest, _base, _add,
221 _shiftAmt, _shiftType, _index)
222 {}
223
224 std::string
225 generateDisassembly(Addr pc, const SymbolTable *symtab) const
226 {
227 std::stringstream ss;
228 this->printInst(ss, MemoryNew::AddrMd_PostIndex);
228 this->printInst(ss, Memory::AddrMd_PostIndex);
229 return ss.str();
230 }
231};
232}
233
234#endif //__ARCH_ARM_INSTS_MEM_HH__
229 return ss.str();
230 }
231};
232}
233
234#endif //__ARCH_ARM_INSTS_MEM_HH__