1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_MEM_HH__
43#define __ARCH_ARM_MEM_HH__
44
45#include "arch/arm/insts/pred_inst.hh"
46
47namespace ArmISA
48{
49
50class Swap : public PredOp
51{
52 protected:
53 IntRegIndex dest;
54 IntRegIndex op1;
55 IntRegIndex base;
56
57 Swap(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
58 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _base)
59 : PredOp(mnem, _machInst, __opClass),
60 dest(_dest), op1(_op1), base(_base)
61 {}
62
63 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
64};
65
66class MightBeMicro : public PredOp
67{
68 protected:
69 MightBeMicro(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
70 : PredOp(mnem, _machInst, __opClass)
71 {}
72
73 void
74 advancePC(PCState &pcState) const
75 {
76 if (flags[IsLastMicroop]) {
77 pcState.uEnd();
78 } else if (flags[IsMicroop]) {
79 pcState.uAdvance();
80 } else {
81 pcState.advance();
82 }
83 }
84};
85
86// The address is a base register plus an immediate.
87class RfeOp : public MightBeMicro
88{
89 public:
90 enum AddrMode {
91 DecrementAfter,
92 DecrementBefore,
93 IncrementAfter,
94 IncrementBefore
95 };
96 protected:
97 IntRegIndex base;
98 AddrMode mode;
99 bool wb;
100 IntRegIndex ura, urb, urc;
101 static const unsigned numMicroops = 3;
102
103 StaticInstPtr *uops;
104
105 RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
106 IntRegIndex _base, AddrMode _mode, bool _wb)
107 : MightBeMicro(mnem, _machInst, __opClass),
108 base(_base), mode(_mode), wb(_wb),
109 ura(INTREG_UREG0), urb(INTREG_UREG1),
110 urc(INTREG_UREG2),
111 uops(NULL)
112 {}
113
114 virtual
115 ~RfeOp()
116 {
117 delete [] uops;
118 }
119
120 StaticInstPtr
121 fetchMicroop(MicroPC microPC) const
122 {
123 assert(uops != NULL && microPC < numMicroops);
124 return uops[microPC];
125 }
126
127 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
128};
129
130// The address is a base register plus an immediate.
131class SrsOp : public MightBeMicro
132{
133 public:
134 enum AddrMode {
135 DecrementAfter,
136 DecrementBefore,
137 IncrementAfter,
138 IncrementBefore
139 };
140 protected:
141 uint32_t regMode;
142 AddrMode mode;
143 bool wb;
144 static const unsigned numMicroops = 2;
145
146 StaticInstPtr *uops;
147
148 SrsOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
149 uint32_t _regMode, AddrMode _mode, bool _wb)
150 : MightBeMicro(mnem, _machInst, __opClass),
151 regMode(_regMode), mode(_mode), wb(_wb), uops(NULL)
152 {}
153
154 virtual
155 ~SrsOp()
156 {
157 delete [] uops;
158 }
159
160 StaticInstPtr
161 fetchMicroop(MicroPC microPC) const
162 {
163 assert(uops != NULL && microPC < numMicroops);
164 return uops[microPC];
165 }
166
167 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
168};
169
170class Memory : public MightBeMicro
171{
172 public:
173 enum AddrMode {
174 AddrMd_Offset,
175 AddrMd_PreIndex,
176 AddrMd_PostIndex
177 };
178
179 protected:
180
181 IntRegIndex dest;
182 IntRegIndex base;
183 bool add;
184 static const unsigned numMicroops = 3;
185
186 StaticInstPtr *uops;
187
188 Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
189 IntRegIndex _dest, IntRegIndex _base, bool _add)
190 : MightBeMicro(mnem, _machInst, __opClass),
191 dest(_dest), base(_base), add(_add), uops(NULL)
192 {}
193
194 virtual
195 ~Memory()
196 {
197 delete [] uops;
198 }
199
200 StaticInstPtr
201 fetchMicroop(MicroPC microPC) const
202 {
203 assert(uops != NULL && microPC < numMicroops);
204 return uops[microPC];
205 }
206
207 virtual void
208 printOffset(std::ostream &os) const
209 {}
210
211 virtual void
212 printDest(std::ostream &os) const
213 {
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_MEM_HH__
43#define __ARCH_ARM_MEM_HH__
44
45#include "arch/arm/insts/pred_inst.hh"
46
47namespace ArmISA
48{
49
50class Swap : public PredOp
51{
52 protected:
53 IntRegIndex dest;
54 IntRegIndex op1;
55 IntRegIndex base;
56
57 Swap(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
58 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _base)
59 : PredOp(mnem, _machInst, __opClass),
60 dest(_dest), op1(_op1), base(_base)
61 {}
62
63 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
64};
65
66class MightBeMicro : public PredOp
67{
68 protected:
69 MightBeMicro(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
70 : PredOp(mnem, _machInst, __opClass)
71 {}
72
73 void
74 advancePC(PCState &pcState) const
75 {
76 if (flags[IsLastMicroop]) {
77 pcState.uEnd();
78 } else if (flags[IsMicroop]) {
79 pcState.uAdvance();
80 } else {
81 pcState.advance();
82 }
83 }
84};
85
86// The address is a base register plus an immediate.
87class RfeOp : public MightBeMicro
88{
89 public:
90 enum AddrMode {
91 DecrementAfter,
92 DecrementBefore,
93 IncrementAfter,
94 IncrementBefore
95 };
96 protected:
97 IntRegIndex base;
98 AddrMode mode;
99 bool wb;
100 IntRegIndex ura, urb, urc;
101 static const unsigned numMicroops = 3;
102
103 StaticInstPtr *uops;
104
105 RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
106 IntRegIndex _base, AddrMode _mode, bool _wb)
107 : MightBeMicro(mnem, _machInst, __opClass),
108 base(_base), mode(_mode), wb(_wb),
109 ura(INTREG_UREG0), urb(INTREG_UREG1),
110 urc(INTREG_UREG2),
111 uops(NULL)
112 {}
113
114 virtual
115 ~RfeOp()
116 {
117 delete [] uops;
118 }
119
120 StaticInstPtr
121 fetchMicroop(MicroPC microPC) const
122 {
123 assert(uops != NULL && microPC < numMicroops);
124 return uops[microPC];
125 }
126
127 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
128};
129
130// The address is a base register plus an immediate.
131class SrsOp : public MightBeMicro
132{
133 public:
134 enum AddrMode {
135 DecrementAfter,
136 DecrementBefore,
137 IncrementAfter,
138 IncrementBefore
139 };
140 protected:
141 uint32_t regMode;
142 AddrMode mode;
143 bool wb;
144 static const unsigned numMicroops = 2;
145
146 StaticInstPtr *uops;
147
148 SrsOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
149 uint32_t _regMode, AddrMode _mode, bool _wb)
150 : MightBeMicro(mnem, _machInst, __opClass),
151 regMode(_regMode), mode(_mode), wb(_wb), uops(NULL)
152 {}
153
154 virtual
155 ~SrsOp()
156 {
157 delete [] uops;
158 }
159
160 StaticInstPtr
161 fetchMicroop(MicroPC microPC) const
162 {
163 assert(uops != NULL && microPC < numMicroops);
164 return uops[microPC];
165 }
166
167 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
168};
169
170class Memory : public MightBeMicro
171{
172 public:
173 enum AddrMode {
174 AddrMd_Offset,
175 AddrMd_PreIndex,
176 AddrMd_PostIndex
177 };
178
179 protected:
180
181 IntRegIndex dest;
182 IntRegIndex base;
183 bool add;
184 static const unsigned numMicroops = 3;
185
186 StaticInstPtr *uops;
187
188 Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
189 IntRegIndex _dest, IntRegIndex _base, bool _add)
190 : MightBeMicro(mnem, _machInst, __opClass),
191 dest(_dest), base(_base), add(_add), uops(NULL)
192 {}
193
194 virtual
195 ~Memory()
196 {
197 delete [] uops;
198 }
199
200 StaticInstPtr
201 fetchMicroop(MicroPC microPC) const
202 {
203 assert(uops != NULL && microPC < numMicroops);
204 return uops[microPC];
205 }
206
207 virtual void
208 printOffset(std::ostream &os) const
209 {}
210
211 virtual void
212 printDest(std::ostream &os) const
213 {
|
345 }
346};
347
348template<class Base>
349class MemoryOffset : public Base
350{
351 protected:
352 MemoryOffset(const char *mnem, ExtMachInst _machInst,
353 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
354 bool _add, int32_t _imm)
355 : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
356 {}
357
358 MemoryOffset(const char *mnem, ExtMachInst _machInst,
359 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
360 bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
361 IntRegIndex _index)
362 : Base(mnem, _machInst, __opClass, _dest, _base, _add,
363 _shiftAmt, _shiftType, _index)
364 {}
365
366 MemoryOffset(const char *mnem, ExtMachInst _machInst,
367 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
368 IntRegIndex _base, bool _add, int32_t _imm)
369 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
370 {}
371
372 MemoryOffset(const char *mnem, ExtMachInst _machInst,
373 OpClass __opClass, IntRegIndex _result,
374 IntRegIndex _dest, IntRegIndex _dest2,
375 IntRegIndex _base, bool _add, int32_t _imm)
376 : Base(mnem, _machInst, __opClass, _result,
377 _dest, _dest2, _base, _add, _imm)
378 {}
379
380 MemoryOffset(const char *mnem, ExtMachInst _machInst,
381 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
382 IntRegIndex _base, bool _add,
383 int32_t _shiftAmt, ArmShiftType _shiftType,
384 IntRegIndex _index)
385 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
386 _shiftAmt, _shiftType, _index)
387 {}
388
389 std::string
390 generateDisassembly(Addr pc, const SymbolTable *symtab) const
391 {
392 std::stringstream ss;
393 this->printInst(ss, Memory::AddrMd_Offset);
394 return ss.str();
395 }
396};
397
398template<class Base>
399class MemoryPreIndex : public Base
400{
401 protected:
402 MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
403 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
404 bool _add, int32_t _imm)
405 : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
406 {}
407
408 MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
409 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
410 bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
411 IntRegIndex _index)
412 : Base(mnem, _machInst, __opClass, _dest, _base, _add,
413 _shiftAmt, _shiftType, _index)
414 {}
415
416 MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
417 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
418 IntRegIndex _base, bool _add, int32_t _imm)
419 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
420 {}
421
422 MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
423 OpClass __opClass, IntRegIndex _result,
424 IntRegIndex _dest, IntRegIndex _dest2,
425 IntRegIndex _base, bool _add, int32_t _imm)
426 : Base(mnem, _machInst, __opClass, _result,
427 _dest, _dest2, _base, _add, _imm)
428 {}
429
430 MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
431 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
432 IntRegIndex _base, bool _add,
433 int32_t _shiftAmt, ArmShiftType _shiftType,
434 IntRegIndex _index)
435 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
436 _shiftAmt, _shiftType, _index)
437 {}
438
439 std::string
440 generateDisassembly(Addr pc, const SymbolTable *symtab) const
441 {
442 std::stringstream ss;
443 this->printInst(ss, Memory::AddrMd_PreIndex);
444 return ss.str();
445 }
446};
447
448template<class Base>
449class MemoryPostIndex : public Base
450{
451 protected:
452 MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
453 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
454 bool _add, int32_t _imm)
455 : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
456 {}
457
458 MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
459 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
460 bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
461 IntRegIndex _index)
462 : Base(mnem, _machInst, __opClass, _dest, _base, _add,
463 _shiftAmt, _shiftType, _index)
464 {}
465
466 MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
467 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
468 IntRegIndex _base, bool _add, int32_t _imm)
469 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
470 {}
471
472 MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
473 OpClass __opClass, IntRegIndex _result,
474 IntRegIndex _dest, IntRegIndex _dest2,
475 IntRegIndex _base, bool _add, int32_t _imm)
476 : Base(mnem, _machInst, __opClass, _result,
477 _dest, _dest2, _base, _add, _imm)
478 {}
479
480 MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
481 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
482 IntRegIndex _base, bool _add,
483 int32_t _shiftAmt, ArmShiftType _shiftType,
484 IntRegIndex _index)
485 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
486 _shiftAmt, _shiftType, _index)
487 {}
488
489 std::string
490 generateDisassembly(Addr pc, const SymbolTable *symtab) const
491 {
492 std::stringstream ss;
493 this->printInst(ss, Memory::AddrMd_PostIndex);
494 return ss.str();
495 }
496};
497}
498
499#endif //__ARCH_ARM_INSTS_MEM_HH__
| 345 }
346};
347
348template<class Base>
349class MemoryOffset : public Base
350{
351 protected:
352 MemoryOffset(const char *mnem, ExtMachInst _machInst,
353 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
354 bool _add, int32_t _imm)
355 : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
356 {}
357
358 MemoryOffset(const char *mnem, ExtMachInst _machInst,
359 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
360 bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
361 IntRegIndex _index)
362 : Base(mnem, _machInst, __opClass, _dest, _base, _add,
363 _shiftAmt, _shiftType, _index)
364 {}
365
366 MemoryOffset(const char *mnem, ExtMachInst _machInst,
367 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
368 IntRegIndex _base, bool _add, int32_t _imm)
369 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
370 {}
371
372 MemoryOffset(const char *mnem, ExtMachInst _machInst,
373 OpClass __opClass, IntRegIndex _result,
374 IntRegIndex _dest, IntRegIndex _dest2,
375 IntRegIndex _base, bool _add, int32_t _imm)
376 : Base(mnem, _machInst, __opClass, _result,
377 _dest, _dest2, _base, _add, _imm)
378 {}
379
380 MemoryOffset(const char *mnem, ExtMachInst _machInst,
381 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
382 IntRegIndex _base, bool _add,
383 int32_t _shiftAmt, ArmShiftType _shiftType,
384 IntRegIndex _index)
385 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
386 _shiftAmt, _shiftType, _index)
387 {}
388
389 std::string
390 generateDisassembly(Addr pc, const SymbolTable *symtab) const
391 {
392 std::stringstream ss;
393 this->printInst(ss, Memory::AddrMd_Offset);
394 return ss.str();
395 }
396};
397
398template<class Base>
399class MemoryPreIndex : public Base
400{
401 protected:
402 MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
403 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
404 bool _add, int32_t _imm)
405 : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
406 {}
407
408 MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
409 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
410 bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
411 IntRegIndex _index)
412 : Base(mnem, _machInst, __opClass, _dest, _base, _add,
413 _shiftAmt, _shiftType, _index)
414 {}
415
416 MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
417 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
418 IntRegIndex _base, bool _add, int32_t _imm)
419 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
420 {}
421
422 MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
423 OpClass __opClass, IntRegIndex _result,
424 IntRegIndex _dest, IntRegIndex _dest2,
425 IntRegIndex _base, bool _add, int32_t _imm)
426 : Base(mnem, _machInst, __opClass, _result,
427 _dest, _dest2, _base, _add, _imm)
428 {}
429
430 MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
431 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
432 IntRegIndex _base, bool _add,
433 int32_t _shiftAmt, ArmShiftType _shiftType,
434 IntRegIndex _index)
435 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
436 _shiftAmt, _shiftType, _index)
437 {}
438
439 std::string
440 generateDisassembly(Addr pc, const SymbolTable *symtab) const
441 {
442 std::stringstream ss;
443 this->printInst(ss, Memory::AddrMd_PreIndex);
444 return ss.str();
445 }
446};
447
448template<class Base>
449class MemoryPostIndex : public Base
450{
451 protected:
452 MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
453 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
454 bool _add, int32_t _imm)
455 : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
456 {}
457
458 MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
459 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
460 bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
461 IntRegIndex _index)
462 : Base(mnem, _machInst, __opClass, _dest, _base, _add,
463 _shiftAmt, _shiftType, _index)
464 {}
465
466 MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
467 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
468 IntRegIndex _base, bool _add, int32_t _imm)
469 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
470 {}
471
472 MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
473 OpClass __opClass, IntRegIndex _result,
474 IntRegIndex _dest, IntRegIndex _dest2,
475 IntRegIndex _base, bool _add, int32_t _imm)
476 : Base(mnem, _machInst, __opClass, _result,
477 _dest, _dest2, _base, _add, _imm)
478 {}
479
480 MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
481 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
482 IntRegIndex _base, bool _add,
483 int32_t _shiftAmt, ArmShiftType _shiftType,
484 IntRegIndex _index)
485 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
486 _shiftAmt, _shiftType, _index)
487 {}
488
489 std::string
490 generateDisassembly(Addr pc, const SymbolTable *symtab) const
491 {
492 std::stringstream ss;
493 this->printInst(ss, Memory::AddrMd_PostIndex);
494 return ss.str();
495 }
496};
497}
498
499#endif //__ARCH_ARM_INSTS_MEM_HH__
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