1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
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82 IntRegIndex _base, AddrMode _mode, bool _wb)
83 : PredOp(mnem, _machInst, __opClass),
84 base(_base), mode(_mode), wb(_wb)
85 {}
86
87 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
88};
89
90class Memory : public PredOp
91{
92 public:
93 enum AddrMode {
94 AddrMd_Offset,
95 AddrMd_PreIndex,
96 AddrMd_PostIndex
97 };
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2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
--- 73 unchanged lines hidden (view full) ---
82 IntRegIndex _base, AddrMode _mode, bool _wb)
83 : PredOp(mnem, _machInst, __opClass),
84 base(_base), mode(_mode), wb(_wb)
85 {}
86
87 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
88};
89
90class Memory : public PredOp
91{
92 public:
93 enum AddrMode {
94 AddrMd_Offset,
95 AddrMd_PreIndex,
96 AddrMd_PostIndex
97 };
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