1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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137 {
138 int32_t pImm = imm;
139 if (!add)
140 pImm = -pImm;
141 ccprintf(os, "#%d", pImm);
142 }
143};
144
145// The address is a base register plus an immediate.
146class MemoryDImm : public MemoryImm
147{
148 protected:
149 IntRegIndex dest2;
150
151 MemoryDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
152 IntRegIndex _dest, IntRegIndex _dest2,

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159 printDest(std::ostream &os) const
160 {
161 MemoryImm::printDest(os);
162 os << ", ";
163 printReg(os, dest2);
164 }
165};
166
167// The address is a shifted register plus an immediate
168class MemoryReg : public Memory
169{
170 protected:
171 int32_t shiftAmt;
172 ArmShiftType shiftType;
173 IntRegIndex index;
174

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261
262 MemoryOffset(const char *mnem, ExtMachInst _machInst,
263 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
264 IntRegIndex _base, bool _add, int32_t _imm)
265 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
266 {}
267
268 MemoryOffset(const char *mnem, ExtMachInst _machInst,
269 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
270 IntRegIndex _base, bool _add,
271 int32_t _shiftAmt, ArmShiftType _shiftType,
272 IntRegIndex _index)
273 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
274 _shiftAmt, _shiftType, _index)
275 {}
276

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303
304 MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
305 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
306 IntRegIndex _base, bool _add, int32_t _imm)
307 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
308 {}
309
310 MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
311 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
312 IntRegIndex _base, bool _add,
313 int32_t _shiftAmt, ArmShiftType _shiftType,
314 IntRegIndex _index)
315 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
316 _shiftAmt, _shiftType, _index)
317 {}
318

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345
346 MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
347 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
348 IntRegIndex _base, bool _add, int32_t _imm)
349 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
350 {}
351
352 MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
353 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
354 IntRegIndex _base, bool _add,
355 int32_t _shiftAmt, ArmShiftType _shiftType,
356 IntRegIndex _index)
357 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
358 _shiftAmt, _shiftType, _index)
359 {}
360
361 std::string
362 generateDisassembly(Addr pc, const SymbolTable *symtab) const
363 {
364 std::stringstream ss;
365 this->printInst(ss, Memory::AddrMd_PostIndex);
366 return ss.str();
367 }
368};
369}
370
371#endif //__ARCH_ARM_INSTS_MEM_HH__