1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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83 : PredOp(mnem, _machInst, __opClass),
84 dest(_dest), base(_base), add(_add)
85 {}
86
87 virtual void
88 printOffset(std::ostream &os) const
89 {}
90
91 void printInst(std::ostream &os, AddrMode addrMode) const;
92};
93
94// The address is a base register plus an immediate.
95class MemoryImm : public Memory
96{
97 protected:
98 int32_t imm;

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107 {
108 int32_t pImm = imm;
109 if (!add)
110 pImm = -pImm;
111 ccprintf(os, "#%d", pImm);
112 }
113};
114
115// The address is a shifted register plus an immediate
116class MemoryReg : public Memory
117{
118 protected:
119 int32_t shiftAmt;
120 ArmShiftType shiftType;
121 IntRegIndex index;
122

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160 ccprintf(os, " ROR #%d", shiftAmt);
161 }
162 break;
163 }
164 }
165 }
166};
167
168template<class Base>
169class MemoryOffset : public Base
170{
171 protected:
172 MemoryOffset(const char *mnem, ExtMachInst _machInst,
173 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
174 bool _add, int32_t _imm)
175 : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
176 {}
177
178 MemoryOffset(const char *mnem, ExtMachInst _machInst,
179 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
180 bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
181 IntRegIndex _index)
182 : Base(mnem, _machInst, __opClass, _dest, _base, _add,
183 _shiftAmt, _shiftType, _index)
184 {}
185
186 std::string
187 generateDisassembly(Addr pc, const SymbolTable *symtab) const
188 {
189 std::stringstream ss;
190 this->printInst(ss, Memory::AddrMd_Offset);
191 return ss.str();
192 }
193};

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205 MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
206 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
207 bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
208 IntRegIndex _index)
209 : Base(mnem, _machInst, __opClass, _dest, _base, _add,
210 _shiftAmt, _shiftType, _index)
211 {}
212
213 std::string
214 generateDisassembly(Addr pc, const SymbolTable *symtab) const
215 {
216 std::stringstream ss;
217 this->printInst(ss, Memory::AddrMd_PreIndex);
218 return ss.str();
219 }
220};

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232 MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
233 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
234 bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
235 IntRegIndex _index)
236 : Base(mnem, _machInst, __opClass, _dest, _base, _add,
237 _shiftAmt, _shiftType, _index)
238 {}
239
240 std::string
241 generateDisassembly(Addr pc, const SymbolTable *symtab) const
242 {
243 std::stringstream ss;
244 this->printInst(ss, Memory::AddrMd_PostIndex);
245 return ss.str();
246 }
247};
248}
249
250#endif //__ARCH_ARM_INSTS_MEM_HH__