1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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137 {
138 int32_t pImm = imm;
139 if (!add)
140 pImm = -pImm;
141 ccprintf(os, "#%d", pImm);
142 }
143};
144
145class MemoryExImm : public MemoryImm
146{
147 protected:
148 IntRegIndex result;
149
150 MemoryExImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
151 IntRegIndex _result, IntRegIndex _dest, IntRegIndex _base,
152 bool _add, int32_t _imm)
153 : MemoryImm(mnem, _machInst, __opClass, _dest, _base, _add, _imm),
154 result(_result)
155 {}
156
157 void
158 printDest(std::ostream &os) const
159 {
160 printReg(os, result);
161 os << ", ";
162 MemoryImm::printDest(os);
163 }
164};
165
166// The address is a base register plus an immediate.
167class MemoryDImm : public MemoryImm
168{
169 protected:
170 IntRegIndex dest2;
171
172 MemoryDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
173 IntRegIndex _dest, IntRegIndex _dest2,

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180 printDest(std::ostream &os) const
181 {
182 MemoryImm::printDest(os);
183 os << ", ";
184 printReg(os, dest2);
185 }
186};
187
188class MemoryExDImm : public MemoryDImm
189{
190 protected:
191 IntRegIndex result;
192
193 MemoryExDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
194 IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2,
195 IntRegIndex _base, bool _add, int32_t _imm)
196 : MemoryDImm(mnem, _machInst, __opClass, _dest, _dest2,
197 _base, _add, _imm), result(_result)
198 {}
199
200 void
201 printDest(std::ostream &os) const
202 {
203 printReg(os, result);
204 os << ", ";
205 MemoryDImm::printDest(os);
206 }
207};
208
209// The address is a shifted register plus an immediate
210class MemoryReg : public Memory
211{
212 protected:
213 int32_t shiftAmt;
214 ArmShiftType shiftType;
215 IntRegIndex index;
216

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303
304 MemoryOffset(const char *mnem, ExtMachInst _machInst,
305 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
306 IntRegIndex _base, bool _add, int32_t _imm)
307 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
308 {}
309
310 MemoryOffset(const char *mnem, ExtMachInst _machInst,
311 OpClass __opClass, IntRegIndex _result,
312 IntRegIndex _dest, IntRegIndex _dest2,
313 IntRegIndex _base, bool _add, int32_t _imm)
314 : Base(mnem, _machInst, __opClass, _result,
315 _dest, _dest2, _base, _add, _imm)
316 {}
317
318 MemoryOffset(const char *mnem, ExtMachInst _machInst,
319 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
320 IntRegIndex _base, bool _add,
321 int32_t _shiftAmt, ArmShiftType _shiftType,
322 IntRegIndex _index)
323 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
324 _shiftAmt, _shiftType, _index)
325 {}
326

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353
354 MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
355 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
356 IntRegIndex _base, bool _add, int32_t _imm)
357 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
358 {}
359
360 MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
361 OpClass __opClass, IntRegIndex _result,
362 IntRegIndex _dest, IntRegIndex _dest2,
363 IntRegIndex _base, bool _add, int32_t _imm)
364 : Base(mnem, _machInst, __opClass, _result,
365 _dest, _dest2, _base, _add, _imm)
366 {}
367
368 MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
369 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
370 IntRegIndex _base, bool _add,
371 int32_t _shiftAmt, ArmShiftType _shiftType,
372 IntRegIndex _index)
373 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
374 _shiftAmt, _shiftType, _index)
375 {}
376

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403
404 MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
405 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
406 IntRegIndex _base, bool _add, int32_t _imm)
407 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
408 {}
409
410 MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
411 OpClass __opClass, IntRegIndex _result,
412 IntRegIndex _dest, IntRegIndex _dest2,
413 IntRegIndex _base, bool _add, int32_t _imm)
414 : Base(mnem, _machInst, __opClass, _result,
415 _dest, _dest2, _base, _add, _imm)
416 {}
417
418 MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
419 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
420 IntRegIndex _base, bool _add,
421 int32_t _shiftAmt, ArmShiftType _shiftType,
422 IntRegIndex _index)
423 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
424 _shiftAmt, _shiftType, _index)
425 {}
426
427 std::string
428 generateDisassembly(Addr pc, const SymbolTable *symtab) const
429 {
430 std::stringstream ss;
431 this->printInst(ss, Memory::AddrMd_PostIndex);
432 return ss.str();
433 }
434};
435}
436
437#endif //__ARCH_ARM_INSTS_MEM_HH__