macromem.hh (8140:7449084b1612) macromem.hh (10037:5cac77888310)
1/*
1/*
2 * Copyright (c) 2010 ARM Limited
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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80 } else if (flags[IsMicroop]) {
81 pcState.uAdvance();
82 } else {
83 pcState.advance();
84 }
85 }
86};
87
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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80 } else if (flags[IsMicroop]) {
81 pcState.uAdvance();
82 } else {
83 pcState.advance();
84 }
85 }
86};
87
88class MicroOpX : public ArmStaticInst
89{
90 protected:
91 MicroOpX(const char *mnem, ExtMachInst machInst, OpClass __opClass)
92 : ArmStaticInst(mnem, machInst, __opClass)
93 {}
94
95 public:
96 void
97 advancePC(PCState &pcState) const
98 {
99 if (flags[IsLastMicroop]) {
100 pcState.uEnd();
101 } else if (flags[IsMicroop]) {
102 pcState.uAdvance();
103 } else {
104 pcState.advance();
105 }
106 }
107};
108
88/**
89 * Microops for Neon loads/stores
90 */
91class MicroNeonMemOp : public MicroOp
92{
93 protected:
94 RegIndex dest, ura;
95 uint32_t imm;

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131 uint32_t _step, unsigned _lane)
132 : MicroNeonMixOp(mnem, machInst, __opClass, _dest, _op1, _step),
133 lane(_lane)
134 {
135 }
136};
137
138/**
109/**
110 * Microops for Neon loads/stores
111 */
112class MicroNeonMemOp : public MicroOp
113{
114 protected:
115 RegIndex dest, ura;
116 uint32_t imm;

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152 uint32_t _step, unsigned _lane)
153 : MicroNeonMixOp(mnem, machInst, __opClass, _dest, _op1, _step),
154 lane(_lane)
155 {
156 }
157};
158
159/**
160 * Microops for AArch64 NEON load/store (de)interleaving
161 */
162class MicroNeonMixOp64 : public MicroOp
163{
164 protected:
165 RegIndex dest, op1;
166 uint8_t eSize, dataSize, numStructElems, numRegs, step;
167
168 MicroNeonMixOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
169 RegIndex _dest, RegIndex _op1, uint8_t _eSize,
170 uint8_t _dataSize, uint8_t _numStructElems,
171 uint8_t _numRegs, uint8_t _step)
172 : MicroOp(mnem, machInst, __opClass), dest(_dest), op1(_op1),
173 eSize(_eSize), dataSize(_dataSize), numStructElems(_numStructElems),
174 numRegs(_numRegs), step(_step)
175 {
176 }
177};
178
179class MicroNeonMixLaneOp64 : public MicroOp
180{
181 protected:
182 RegIndex dest, op1;
183 uint8_t eSize, dataSize, numStructElems, lane, step;
184 bool replicate;
185
186 MicroNeonMixLaneOp64(const char *mnem, ExtMachInst machInst,
187 OpClass __opClass, RegIndex _dest, RegIndex _op1,
188 uint8_t _eSize, uint8_t _dataSize,
189 uint8_t _numStructElems, uint8_t _lane, uint8_t _step,
190 bool _replicate = false)
191 : MicroOp(mnem, machInst, __opClass), dest(_dest), op1(_op1),
192 eSize(_eSize), dataSize(_dataSize), numStructElems(_numStructElems),
193 lane(_lane), step(_step), replicate(_replicate)
194 {
195 }
196};
197
198/**
199 * Base classes for microcoded AArch64 NEON memory instructions.
200 */
201class VldMultOp64 : public PredMacroOp
202{
203 protected:
204 uint8_t eSize, dataSize, numStructElems, numRegs;
205 bool wb;
206
207 VldMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
208 RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
209 uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs,
210 bool wb);
211};
212
213class VstMultOp64 : public PredMacroOp
214{
215 protected:
216 uint8_t eSize, dataSize, numStructElems, numRegs;
217 bool wb;
218
219 VstMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
220 RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
221 uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs,
222 bool wb);
223};
224
225class VldSingleOp64 : public PredMacroOp
226{
227 protected:
228 uint8_t eSize, dataSize, numStructElems, index;
229 bool wb, replicate;
230
231 VldSingleOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
232 RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
233 uint8_t dataSize, uint8_t numStructElems, uint8_t index,
234 bool wb, bool replicate = false);
235};
236
237class VstSingleOp64 : public PredMacroOp
238{
239 protected:
240 uint8_t eSize, dataSize, numStructElems, index;
241 bool wb, replicate;
242
243 VstSingleOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
244 RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
245 uint8_t dataSize, uint8_t numStructElems, uint8_t index,
246 bool wb, bool replicate = false);
247};
248
249/**
139 * Microops of the form
140 * PC = IntRegA
141 * CPSR = IntRegB
142 */
143class MicroSetPCCPSR : public MicroOp
144{
145 protected:
146 IntRegIndex ura, urb, urc;

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175
176/**
177 * Microops of the form IntRegA = IntRegB op Imm
178 */
179class MicroIntImmOp : public MicroOp
180{
181 protected:
182 RegIndex ura, urb;
250 * Microops of the form
251 * PC = IntRegA
252 * CPSR = IntRegB
253 */
254class MicroSetPCCPSR : public MicroOp
255{
256 protected:
257 IntRegIndex ura, urb, urc;

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286
287/**
288 * Microops of the form IntRegA = IntRegB op Imm
289 */
290class MicroIntImmOp : public MicroOp
291{
292 protected:
293 RegIndex ura, urb;
183 uint32_t imm;
294 int32_t imm;
184
185 MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
295
296 MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
186 RegIndex _ura, RegIndex _urb, uint32_t _imm)
297 RegIndex _ura, RegIndex _urb, int32_t _imm)
187 : MicroOp(mnem, machInst, __opClass),
188 ura(_ura), urb(_urb), imm(_imm)
189 {
190 }
191
192 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
193};
194
298 : MicroOp(mnem, machInst, __opClass),
299 ura(_ura), urb(_urb), imm(_imm)
300 {
301 }
302
303 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
304};
305
306class MicroIntImmXOp : public MicroOpX
307{
308 protected:
309 RegIndex ura, urb;
310 int64_t imm;
311
312 MicroIntImmXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
313 RegIndex _ura, RegIndex _urb, int64_t _imm)
314 : MicroOpX(mnem, machInst, __opClass),
315 ura(_ura), urb(_urb), imm(_imm)
316 {
317 }
318
319 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
320};
321
195/**
196 * Microops of the form IntRegA = IntRegB op IntRegC
197 */
198class MicroIntOp : public MicroOp
199{
200 protected:
201 RegIndex ura, urb, urc;
202
203 MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
204 RegIndex _ura, RegIndex _urb, RegIndex _urc)
205 : MicroOp(mnem, machInst, __opClass),
206 ura(_ura), urb(_urb), urc(_urc)
207 {
208 }
209
210 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
211};
212
322/**
323 * Microops of the form IntRegA = IntRegB op IntRegC
324 */
325class MicroIntOp : public MicroOp
326{
327 protected:
328 RegIndex ura, urb, urc;
329
330 MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
331 RegIndex _ura, RegIndex _urb, RegIndex _urc)
332 : MicroOp(mnem, machInst, __opClass),
333 ura(_ura), urb(_urb), urc(_urc)
334 {
335 }
336
337 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
338};
339
340class MicroIntRegXOp : public MicroOp
341{
342 protected:
343 RegIndex ura, urb, urc;
344 ArmExtendType type;
345 uint32_t shiftAmt;
346
347 MicroIntRegXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
348 RegIndex _ura, RegIndex _urb, RegIndex _urc,
349 ArmExtendType _type, uint32_t _shiftAmt)
350 : MicroOp(mnem, machInst, __opClass),
351 ura(_ura), urb(_urb), urc(_urc),
352 type(_type), shiftAmt(_shiftAmt)
353 {
354 }
355
356 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
357};
358
213/**
214 * Microops of the form IntRegA = IntRegB op shifted IntRegC
215 */
216class MicroIntRegOp : public MicroOp
217{
218 protected:
219 RegIndex ura, urb, urc;
220 int32_t shiftAmt;

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256{
257 protected:
258 MacroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
259 IntRegIndex rn, bool index, bool up, bool user,
260 bool writeback, bool load, uint32_t reglist);
261};
262
263/**
359/**
360 * Microops of the form IntRegA = IntRegB op shifted IntRegC
361 */
362class MicroIntRegOp : public MicroOp
363{
364 protected:
365 RegIndex ura, urb, urc;
366 int32_t shiftAmt;

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402{
403 protected:
404 MacroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
405 IntRegIndex rn, bool index, bool up, bool user,
406 bool writeback, bool load, uint32_t reglist);
407};
408
409/**
410 * Base class for pair load/store instructions.
411 */
412class PairMemOp : public PredMacroOp
413{
414 public:
415 enum AddrMode {
416 AddrMd_Offset,
417 AddrMd_PreIndex,
418 AddrMd_PostIndex
419 };
420
421 protected:
422 PairMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
423 uint32_t size, bool fp, bool load, bool noAlloc, bool signExt,
424 bool exclusive, bool acrel, int64_t imm, AddrMode mode,
425 IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2);
426};
427
428class BigFpMemImmOp : public PredMacroOp
429{
430 protected:
431 BigFpMemImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
432 bool load, IntRegIndex dest, IntRegIndex base, int64_t imm);
433};
434
435class BigFpMemPostOp : public PredMacroOp
436{
437 protected:
438 BigFpMemPostOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
439 bool load, IntRegIndex dest, IntRegIndex base, int64_t imm);
440};
441
442class BigFpMemPreOp : public PredMacroOp
443{
444 protected:
445 BigFpMemPreOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
446 bool load, IntRegIndex dest, IntRegIndex base, int64_t imm);
447};
448
449class BigFpMemRegOp : public PredMacroOp
450{
451 protected:
452 BigFpMemRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
453 bool load, IntRegIndex dest, IntRegIndex base,
454 IntRegIndex offset, ArmExtendType type, int64_t imm);
455};
456
457class BigFpMemLitOp : public PredMacroOp
458{
459 protected:
460 BigFpMemLitOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
461 IntRegIndex dest, int64_t imm);
462};
463
464/**
264 * Base classes for microcoded integer memory instructions.
265 */
266class VldMultOp : public PredMacroOp
267{
268 protected:
269 VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
270 unsigned elems, RegIndex rn, RegIndex vd, unsigned regs,
271 unsigned inc, uint32_t size, uint32_t align, RegIndex rm);

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466 */
467class VldMultOp : public PredMacroOp
468{
469 protected:
470 VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
471 unsigned elems, RegIndex rn, RegIndex vd, unsigned regs,
472 unsigned inc, uint32_t size, uint32_t align, RegIndex rm);

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