macromem.hh (7639:8c09b7ff5b57) macromem.hh (7646:a444dbee8c07)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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123 MicroNeonMixLaneOp(const char *mnem, ExtMachInst machInst,
124 OpClass __opClass, RegIndex _dest, RegIndex _op1,
125 uint32_t _step, unsigned _lane)
126 : MicroNeonMixOp(mnem, machInst, __opClass, _dest, _op1, _step),
127 lane(_lane)
128 {
129 }
130};
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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123 MicroNeonMixLaneOp(const char *mnem, ExtMachInst machInst,
124 OpClass __opClass, RegIndex _dest, RegIndex _op1,
125 uint32_t _step, unsigned _lane)
126 : MicroNeonMixOp(mnem, machInst, __opClass, _dest, _op1, _step),
127 lane(_lane)
128 {
129 }
130};
131/**
132 * Microops of the form IntRegA = IntRegB
133 */
134class MicroIntMov : public MicroOp
135{
136 protected:
137 RegIndex ura, urb;
131
138
139 MicroIntMov(const char *mnem, ExtMachInst machInst, OpClass __opClass,
140 RegIndex _ura, RegIndex _urb)
141 : MicroOp(mnem, machInst, __opClass),
142 ura(_ura), urb(_urb)
143 {
144 }
145
146 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
147};
148
132/**
133 * Microops of the form IntRegA = IntRegB op Imm
134 */
135class MicroIntImmOp : public MicroOp
136{
137 protected:
138 RegIndex ura, urb;
149/**
150 * Microops of the form IntRegA = IntRegB op Imm
151 */
152class MicroIntImmOp : public MicroOp
153{
154 protected:
155 RegIndex ura, urb;
139 uint8_t imm;
156 uint32_t imm;
140
141 MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
157
158 MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
142 RegIndex _ura, RegIndex _urb, uint8_t _imm)
159 RegIndex _ura, RegIndex _urb, uint32_t _imm)
143 : MicroOp(mnem, machInst, __opClass),
144 ura(_ura), urb(_urb), imm(_imm)
145 {
146 }
147
148 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
149};
150

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162 ura(_ura), urb(_urb), urc(_urc)
163 {
164 }
165
166 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
167};
168
169/**
160 : MicroOp(mnem, machInst, __opClass),
161 ura(_ura), urb(_urb), imm(_imm)
162 {
163 }
164
165 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
166};
167

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179 ura(_ura), urb(_urb), urc(_urc)
180 {
181 }
182
183 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
184};
185
186/**
187 * Microops of the form IntRegA = IntRegB op shifted IntRegC
188 */
189class MicroIntRegOp : public MicroOp
190{
191 protected:
192 RegIndex ura, urb, urc;
193 int32_t shiftAmt;
194 ArmShiftType shiftType;
195
196 MicroIntRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
197 RegIndex _ura, RegIndex _urb, RegIndex _urc,
198 int32_t _shiftAmt, ArmShiftType _shiftType)
199 : MicroOp(mnem, machInst, __opClass),
200 ura(_ura), urb(_urb), urc(_urc),
201 shiftAmt(_shiftAmt), shiftType(_shiftType)
202 {
203 }
204};
205
206/**
170 * Memory microops which use IntReg + Imm addressing
171 */
172class MicroMemOp : public MicroIntImmOp
173{
174 protected:
175 bool up;
176 unsigned memAccessFlags;
177

--- 75 unchanged lines hidden --- 		207 * Memory microops which use IntReg + Imm addressing
208 */
209class MicroMemOp : public MicroIntImmOp
210{
211 protected:
212 bool up;
213 unsigned memAccessFlags;
214

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