macromem.hh (10346:d96b61d843b2) | macromem.hh (12616:4b463b4dc098) |
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1/* 2 * Copyright (c) 2010-2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 59 unchanged lines hidden (view full) --- 68 protected: 69 MicroOp(const char *mnem, ExtMachInst machInst, OpClass __opClass) 70 : PredOp(mnem, machInst, __opClass) 71 { 72 } 73 74 public: 75 void | 1/* 2 * Copyright (c) 2010-2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 59 unchanged lines hidden (view full) --- 68 protected: 69 MicroOp(const char *mnem, ExtMachInst machInst, OpClass __opClass) 70 : PredOp(mnem, machInst, __opClass) 71 { 72 } 73 74 public: 75 void |
76 advancePC(PCState &pcState) const | 76 advancePC(PCState &pcState) const override |
77 { 78 if (flags[IsLastMicroop]) { 79 pcState.uEnd(); 80 } else if (flags[IsMicroop]) { 81 pcState.uAdvance(); 82 } else { 83 pcState.advance(); 84 } --- 4 unchanged lines hidden (view full) --- 89{ 90 protected: 91 MicroOpX(const char *mnem, ExtMachInst machInst, OpClass __opClass) 92 : ArmStaticInst(mnem, machInst, __opClass) 93 {} 94 95 public: 96 void | 77 { 78 if (flags[IsLastMicroop]) { 79 pcState.uEnd(); 80 } else if (flags[IsMicroop]) { 81 pcState.uAdvance(); 82 } else { 83 pcState.advance(); 84 } --- 4 unchanged lines hidden (view full) --- 89{ 90 protected: 91 MicroOpX(const char *mnem, ExtMachInst machInst, OpClass __opClass) 92 : ArmStaticInst(mnem, machInst, __opClass) 93 {} 94 95 public: 96 void |
97 advancePC(PCState &pcState) const | 97 advancePC(PCState &pcState) const override |
98 { 99 if (flags[IsLastMicroop]) { 100 pcState.uEnd(); 101 } else if (flags[IsMicroop]) { 102 pcState.uAdvance(); 103 } else { 104 pcState.advance(); 105 } --- 152 unchanged lines hidden (view full) --- 258 259 MicroSetPCCPSR(const char *mnem, ExtMachInst machInst, OpClass __opClass, 260 IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc) 261 : MicroOp(mnem, machInst, __opClass), 262 ura(_ura), urb(_urb), urc(_urc) 263 { 264 } 265 | 98 { 99 if (flags[IsLastMicroop]) { 100 pcState.uEnd(); 101 } else if (flags[IsMicroop]) { 102 pcState.uAdvance(); 103 } else { 104 pcState.advance(); 105 } --- 152 unchanged lines hidden (view full) --- 258 259 MicroSetPCCPSR(const char *mnem, ExtMachInst machInst, OpClass __opClass, 260 IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc) 261 : MicroOp(mnem, machInst, __opClass), 262 ura(_ura), urb(_urb), urc(_urc) 263 { 264 } 265 |
266 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; | 266 std::string generateDisassembly( 267 Addr pc, const SymbolTable *symtab) const override; |
267}; 268 269/** 270 * Microops of the form IntRegA = IntRegB 271 */ 272class MicroIntMov : public MicroOp 273{ 274 protected: 275 RegIndex ura, urb; 276 277 MicroIntMov(const char *mnem, ExtMachInst machInst, OpClass __opClass, 278 RegIndex _ura, RegIndex _urb) 279 : MicroOp(mnem, machInst, __opClass), 280 ura(_ura), urb(_urb) 281 { 282 } 283 | 268}; 269 270/** 271 * Microops of the form IntRegA = IntRegB 272 */ 273class MicroIntMov : public MicroOp 274{ 275 protected: 276 RegIndex ura, urb; 277 278 MicroIntMov(const char *mnem, ExtMachInst machInst, OpClass __opClass, 279 RegIndex _ura, RegIndex _urb) 280 : MicroOp(mnem, machInst, __opClass), 281 ura(_ura), urb(_urb) 282 { 283 } 284 |
284 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; | 285 std::string generateDisassembly( 286 Addr pc, const SymbolTable *symtab) const override; |
285}; 286 287/** 288 * Microops of the form IntRegA = IntRegB op Imm 289 */ 290class MicroIntImmOp : public MicroOp 291{ 292 protected: 293 RegIndex ura, urb; 294 int32_t imm; 295 296 MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 297 RegIndex _ura, RegIndex _urb, int32_t _imm) 298 : MicroOp(mnem, machInst, __opClass), 299 ura(_ura), urb(_urb), imm(_imm) 300 { 301 } 302 | 287}; 288 289/** 290 * Microops of the form IntRegA = IntRegB op Imm 291 */ 292class MicroIntImmOp : public MicroOp 293{ 294 protected: 295 RegIndex ura, urb; 296 int32_t imm; 297 298 MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 299 RegIndex _ura, RegIndex _urb, int32_t _imm) 300 : MicroOp(mnem, machInst, __opClass), 301 ura(_ura), urb(_urb), imm(_imm) 302 { 303 } 304 |
303 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; | 305 std::string generateDisassembly( 306 Addr pc, const SymbolTable *symtab) const override; |
304}; 305 306class MicroIntImmXOp : public MicroOpX 307{ 308 protected: 309 RegIndex ura, urb; 310 int64_t imm; 311 312 MicroIntImmXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 313 RegIndex _ura, RegIndex _urb, int64_t _imm) 314 : MicroOpX(mnem, machInst, __opClass), 315 ura(_ura), urb(_urb), imm(_imm) 316 { 317 } 318 | 307}; 308 309class MicroIntImmXOp : public MicroOpX 310{ 311 protected: 312 RegIndex ura, urb; 313 int64_t imm; 314 315 MicroIntImmXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 316 RegIndex _ura, RegIndex _urb, int64_t _imm) 317 : MicroOpX(mnem, machInst, __opClass), 318 ura(_ura), urb(_urb), imm(_imm) 319 { 320 } 321 |
319 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; | 322 std::string generateDisassembly( 323 Addr pc, const SymbolTable *symtab) const override; |
320}; 321 322/** 323 * Microops of the form IntRegA = IntRegB op IntRegC 324 */ 325class MicroIntOp : public MicroOp 326{ 327 protected: 328 RegIndex ura, urb, urc; 329 330 MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 331 RegIndex _ura, RegIndex _urb, RegIndex _urc) 332 : MicroOp(mnem, machInst, __opClass), 333 ura(_ura), urb(_urb), urc(_urc) 334 { 335 } 336 | 324}; 325 326/** 327 * Microops of the form IntRegA = IntRegB op IntRegC 328 */ 329class MicroIntOp : public MicroOp 330{ 331 protected: 332 RegIndex ura, urb, urc; 333 334 MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 335 RegIndex _ura, RegIndex _urb, RegIndex _urc) 336 : MicroOp(mnem, machInst, __opClass), 337 ura(_ura), urb(_urb), urc(_urc) 338 { 339 } 340 |
337 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; | 341 std::string generateDisassembly( 342 Addr pc, const SymbolTable *symtab) const override; |
338}; 339 340class MicroIntRegXOp : public MicroOp 341{ 342 protected: 343 RegIndex ura, urb, urc; 344 ArmExtendType type; 345 uint32_t shiftAmt; 346 347 MicroIntRegXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 348 RegIndex _ura, RegIndex _urb, RegIndex _urc, 349 ArmExtendType _type, uint32_t _shiftAmt) 350 : MicroOp(mnem, machInst, __opClass), 351 ura(_ura), urb(_urb), urc(_urc), 352 type(_type), shiftAmt(_shiftAmt) 353 { 354 } 355 | 343}; 344 345class MicroIntRegXOp : public MicroOp 346{ 347 protected: 348 RegIndex ura, urb, urc; 349 ArmExtendType type; 350 uint32_t shiftAmt; 351 352 MicroIntRegXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 353 RegIndex _ura, RegIndex _urb, RegIndex _urc, 354 ArmExtendType _type, uint32_t _shiftAmt) 355 : MicroOp(mnem, machInst, __opClass), 356 ura(_ura), urb(_urb), urc(_urc), 357 type(_type), shiftAmt(_shiftAmt) 358 { 359 } 360 |
356 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; | 361 std::string generateDisassembly( 362 Addr pc, const SymbolTable *symtab) const override; |
357}; 358 359/** 360 * Microops of the form IntRegA = IntRegB op shifted IntRegC 361 */ 362class MicroIntRegOp : public MicroOp 363{ 364 protected: --- 22 unchanged lines hidden (view full) --- 387 388 MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 389 RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm) 390 : MicroIntImmOp(mnem, machInst, __opClass, _ura, _urb, _imm), 391 up(_up), memAccessFlags(TLB::MustBeOne | TLB::AlignWord) 392 { 393 } 394 | 363}; 364 365/** 366 * Microops of the form IntRegA = IntRegB op shifted IntRegC 367 */ 368class MicroIntRegOp : public MicroOp 369{ 370 protected: --- 22 unchanged lines hidden (view full) --- 393 394 MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 395 RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm) 396 : MicroIntImmOp(mnem, machInst, __opClass, _ura, _urb, _imm), 397 up(_up), memAccessFlags(TLB::MustBeOne | TLB::AlignWord) 398 { 399 } 400 |
395 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; | 401 std::string generateDisassembly( 402 Addr pc, const SymbolTable *symtab) const override; |
396}; 397 398class MicroMemPairOp : public MicroOp 399{ 400 protected: 401 RegIndex dest, dest2, urb; 402 bool up; 403 int32_t imm; 404 unsigned memAccessFlags; 405 406 MicroMemPairOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 407 RegIndex _dreg1, RegIndex _dreg2, RegIndex _base, 408 bool _up, uint8_t _imm) 409 : MicroOp(mnem, machInst, __opClass), 410 dest(_dreg1), dest2(_dreg2), urb(_base), up(_up), imm(_imm), 411 memAccessFlags(TLB::MustBeOne | TLB::AlignWord) 412 { 413 } 414 | 403}; 404 405class MicroMemPairOp : public MicroOp 406{ 407 protected: 408 RegIndex dest, dest2, urb; 409 bool up; 410 int32_t imm; 411 unsigned memAccessFlags; 412 413 MicroMemPairOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 414 RegIndex _dreg1, RegIndex _dreg2, RegIndex _base, 415 bool _up, uint8_t _imm) 416 : MicroOp(mnem, machInst, __opClass), 417 dest(_dreg1), dest2(_dreg2), urb(_base), up(_up), imm(_imm), 418 memAccessFlags(TLB::MustBeOne | TLB::AlignWord) 419 { 420 } 421 |
415 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; | 422 std::string generateDisassembly( 423 Addr pc, const SymbolTable *symtab) const override; |
416}; 417 418/** 419 * Base class for microcoded integer memory instructions. 420 */ 421class MacroMemOp : public PredMacroOp 422{ 423 protected: --- 114 unchanged lines hidden --- | 424}; 425 426/** 427 * Base class for microcoded integer memory instructions. 428 */ 429class MacroMemOp : public PredMacroOp 430{ 431 protected: --- 114 unchanged lines hidden --- |