1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 66 unchanged lines hidden (view full) --- 75 void 76 setDelayedCommit() 77 { 78 flags[IsDelayedCommit] = true; 79 } 80}; 81 82/** |
83 * Microops for Neon loads/stores 84 */ 85class MicroNeonMemOp : public MicroOp 86{ 87 protected: 88 RegIndex dest, ura; 89 uint32_t imm; 90 unsigned memAccessFlags; 91 92 MicroNeonMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 93 RegIndex _dest, RegIndex _ura, uint32_t _imm) 94 : MicroOp(mnem, machInst, __opClass), 95 dest(_dest), ura(_ura), imm(_imm), 96 memAccessFlags(TLB::MustBeOne) 97 { 98 } 99}; 100 101/** 102 * Microops for Neon load/store (de)interleaving 103 */ 104class MicroNeonMixOp : public MicroOp 105{ 106 protected: 107 RegIndex dest, op1; 108 uint32_t step; 109 110 MicroNeonMixOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 111 RegIndex _dest, RegIndex _op1, uint32_t _step) 112 : MicroOp(mnem, machInst, __opClass), 113 dest(_dest), op1(_op1), step(_step) 114 { 115 } 116}; 117 118class MicroNeonMixLaneOp : public MicroNeonMixOp 119{ 120 protected: 121 unsigned lane; 122 123 MicroNeonMixLaneOp(const char *mnem, ExtMachInst machInst, 124 OpClass __opClass, RegIndex _dest, RegIndex _op1, 125 uint32_t _step, unsigned _lane) 126 : MicroNeonMixOp(mnem, machInst, __opClass, _dest, _op1, _step), 127 lane(_lane) 128 { 129 } 130}; 131 132/** |
133 * Microops of the form IntRegA = IntRegB op Imm 134 */ |
135class MicroIntImmOp : public MicroOp |
136{ 137 protected: 138 RegIndex ura, urb; 139 uint8_t imm; 140 |
141 MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 142 RegIndex _ura, RegIndex _urb, uint8_t _imm) |
143 : MicroOp(mnem, machInst, __opClass), 144 ura(_ura), urb(_urb), imm(_imm) 145 { 146 } 147 148 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 149}; 150 151/** |
152 * Microops of the form IntRegA = IntRegB op IntRegC 153 */ 154class MicroIntOp : public MicroOp 155{ 156 protected: 157 RegIndex ura, urb, urc; 158 159 MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 160 RegIndex _ura, RegIndex _urb, RegIndex _urc) 161 : MicroOp(mnem, machInst, __opClass), 162 ura(_ura), urb(_urb), urc(_urc) 163 { 164 } 165 166 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 167}; 168 169/** |
170 * Memory microops which use IntReg + Imm addressing 171 */ |
172class MicroMemOp : public MicroIntImmOp |
173{ 174 protected: 175 bool up; 176 unsigned memAccessFlags; 177 178 MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 179 RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm) |
180 : MicroIntImmOp(mnem, machInst, __opClass, _ura, _urb, _imm), |
181 up(_up), memAccessFlags(TLB::MustBeOne | TLB::AlignWord) 182 { 183 } 184 185 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 186}; 187 188/** 189 * Base class for microcoded integer memory instructions. 190 */ 191class MacroMemOp : public PredMacroOp 192{ 193 protected: 194 MacroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 195 IntRegIndex rn, bool index, bool up, bool user, 196 bool writeback, bool load, uint32_t reglist); 197}; 198 199/** |
200 * Base classes for microcoded integer memory instructions. 201 */ 202class VldMultOp : public PredMacroOp 203{ 204 protected: 205 VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 206 unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, 207 unsigned inc, uint32_t size, uint32_t align, RegIndex rm); 208}; 209 210class VldSingleOp : public PredMacroOp 211{ 212 protected: 213 VldSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 214 bool all, unsigned elems, RegIndex rn, RegIndex vd, 215 unsigned regs, unsigned inc, uint32_t size, 216 uint32_t align, RegIndex rm, unsigned lane); 217}; 218 219/** 220 * Base class for microcoded integer memory instructions. 221 */ 222class VstMultOp : public PredMacroOp 223{ 224 protected: 225 VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 226 unsigned width, RegIndex rn, RegIndex vd, unsigned regs, 227 unsigned inc, uint32_t size, uint32_t align, RegIndex rm); 228}; 229 230class VstSingleOp : public PredMacroOp 231{ 232 protected: 233 VstSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 234 bool all, unsigned elems, RegIndex rn, RegIndex vd, 235 unsigned regs, unsigned inc, uint32_t size, 236 uint32_t align, RegIndex rm, unsigned lane); 237}; 238 239/** |
240 * Base class for microcoded floating point memory instructions. 241 */ 242class MacroVFPMemOp : public PredMacroOp 243{ 244 protected: 245 MacroVFPMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 246 IntRegIndex rn, RegIndex vd, bool single, bool up, 247 bool writeback, bool load, uint32_t offset); 248}; 249 250} 251 252#endif //__ARCH_ARM_INSTS_MACROMEM_HH__ |