1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 80 unchanged lines hidden (view full) --- 89 uint8_t imm; 90 91 MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 92 RegIndex _ura, RegIndex _urb, uint8_t _imm) 93 : MicroOp(mnem, machInst, __opClass), 94 ura(_ura), urb(_urb), imm(_imm) 95 { 96 } |
97 98 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; |
99}; 100 101/** 102 * Memory microops which use IntReg + Imm addressing 103 */ 104class MicroMemOp : public MicroIntOp 105{ 106 protected: 107 bool up; 108 unsigned memAccessFlags; 109 110 MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 111 RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm) 112 : MicroIntOp(mnem, machInst, __opClass, _ura, _urb, _imm), 113 up(_up), memAccessFlags(TLB::MustBeOne | TLB::AlignWord) 114 { 115 } |
116 117 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; |
118}; 119 120/** 121 * Base class for microcoded integer memory instructions. 122 */ 123class MacroMemOp : public PredMacroOp 124{ 125 protected: --- 19 unchanged lines hidden --- |