1/*
| 1/*
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2 * Copyright (c) 2010 ARM Limited
| 2 * Copyright (c) 2010-2013 ARM Limited
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3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42#ifndef __ARCH_ARM_MACROMEM_HH__ 43#define __ARCH_ARM_MACROMEM_HH__ 44 45#include "arch/arm/insts/pred_inst.hh" 46#include "arch/arm/tlb.hh" 47 48namespace ArmISA 49{ 50 51static inline unsigned int 52number_of_ones(int32_t val) 53{ 54 uint32_t ones = 0; 55 for (int i = 0; i < 32; i++ ) 56 { 57 if ( val & (1<<i) ) 58 ones++; 59 } 60 return ones; 61} 62 63/** 64 * Base class for Memory microops 65 */ 66class MicroOp : public PredOp 67{ 68 protected: 69 MicroOp(const char *mnem, ExtMachInst machInst, OpClass __opClass) 70 : PredOp(mnem, machInst, __opClass) 71 { 72 } 73 74 public: 75 void 76 advancePC(PCState &pcState) const 77 { 78 if (flags[IsLastMicroop]) { 79 pcState.uEnd(); 80 } else if (flags[IsMicroop]) { 81 pcState.uAdvance(); 82 } else { 83 pcState.advance(); 84 } 85 } 86}; 87
| 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42#ifndef __ARCH_ARM_MACROMEM_HH__ 43#define __ARCH_ARM_MACROMEM_HH__ 44 45#include "arch/arm/insts/pred_inst.hh" 46#include "arch/arm/tlb.hh" 47 48namespace ArmISA 49{ 50 51static inline unsigned int 52number_of_ones(int32_t val) 53{ 54 uint32_t ones = 0; 55 for (int i = 0; i < 32; i++ ) 56 { 57 if ( val & (1<<i) ) 58 ones++; 59 } 60 return ones; 61} 62 63/** 64 * Base class for Memory microops 65 */ 66class MicroOp : public PredOp 67{ 68 protected: 69 MicroOp(const char *mnem, ExtMachInst machInst, OpClass __opClass) 70 : PredOp(mnem, machInst, __opClass) 71 { 72 } 73 74 public: 75 void 76 advancePC(PCState &pcState) const 77 { 78 if (flags[IsLastMicroop]) { 79 pcState.uEnd(); 80 } else if (flags[IsMicroop]) { 81 pcState.uAdvance(); 82 } else { 83 pcState.advance(); 84 } 85 } 86}; 87
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| 88class MicroOpX : public ArmStaticInst 89{ 90 protected: 91 MicroOpX(const char *mnem, ExtMachInst machInst, OpClass __opClass) 92 : ArmStaticInst(mnem, machInst, __opClass) 93 {} 94 95 public: 96 void 97 advancePC(PCState &pcState) const 98 { 99 if (flags[IsLastMicroop]) { 100 pcState.uEnd(); 101 } else if (flags[IsMicroop]) { 102 pcState.uAdvance(); 103 } else { 104 pcState.advance(); 105 } 106 } 107}; 108
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88/** 89 * Microops for Neon loads/stores 90 */ 91class MicroNeonMemOp : public MicroOp 92{ 93 protected: 94 RegIndex dest, ura; 95 uint32_t imm; 96 unsigned memAccessFlags; 97 98 MicroNeonMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 99 RegIndex _dest, RegIndex _ura, uint32_t _imm) 100 : MicroOp(mnem, machInst, __opClass), 101 dest(_dest), ura(_ura), imm(_imm), 102 memAccessFlags(TLB::MustBeOne) 103 { 104 } 105}; 106 107/** 108 * Microops for Neon load/store (de)interleaving 109 */ 110class MicroNeonMixOp : public MicroOp 111{ 112 protected: 113 RegIndex dest, op1; 114 uint32_t step; 115 116 MicroNeonMixOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 117 RegIndex _dest, RegIndex _op1, uint32_t _step) 118 : MicroOp(mnem, machInst, __opClass), 119 dest(_dest), op1(_op1), step(_step) 120 { 121 } 122}; 123 124class MicroNeonMixLaneOp : public MicroNeonMixOp 125{ 126 protected: 127 unsigned lane; 128 129 MicroNeonMixLaneOp(const char *mnem, ExtMachInst machInst, 130 OpClass __opClass, RegIndex _dest, RegIndex _op1, 131 uint32_t _step, unsigned _lane) 132 : MicroNeonMixOp(mnem, machInst, __opClass, _dest, _op1, _step), 133 lane(_lane) 134 { 135 } 136}; 137 138/**
| 109/** 110 * Microops for Neon loads/stores 111 */ 112class MicroNeonMemOp : public MicroOp 113{ 114 protected: 115 RegIndex dest, ura; 116 uint32_t imm; 117 unsigned memAccessFlags; 118 119 MicroNeonMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 120 RegIndex _dest, RegIndex _ura, uint32_t _imm) 121 : MicroOp(mnem, machInst, __opClass), 122 dest(_dest), ura(_ura), imm(_imm), 123 memAccessFlags(TLB::MustBeOne) 124 { 125 } 126}; 127 128/** 129 * Microops for Neon load/store (de)interleaving 130 */ 131class MicroNeonMixOp : public MicroOp 132{ 133 protected: 134 RegIndex dest, op1; 135 uint32_t step; 136 137 MicroNeonMixOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 138 RegIndex _dest, RegIndex _op1, uint32_t _step) 139 : MicroOp(mnem, machInst, __opClass), 140 dest(_dest), op1(_op1), step(_step) 141 { 142 } 143}; 144 145class MicroNeonMixLaneOp : public MicroNeonMixOp 146{ 147 protected: 148 unsigned lane; 149 150 MicroNeonMixLaneOp(const char *mnem, ExtMachInst machInst, 151 OpClass __opClass, RegIndex _dest, RegIndex _op1, 152 uint32_t _step, unsigned _lane) 153 : MicroNeonMixOp(mnem, machInst, __opClass, _dest, _op1, _step), 154 lane(_lane) 155 { 156 } 157}; 158 159/**
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| 160 * Microops for AArch64 NEON load/store (de)interleaving 161 */ 162class MicroNeonMixOp64 : public MicroOp 163{ 164 protected: 165 RegIndex dest, op1; 166 uint8_t eSize, dataSize, numStructElems, numRegs, step; 167 168 MicroNeonMixOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, 169 RegIndex _dest, RegIndex _op1, uint8_t _eSize, 170 uint8_t _dataSize, uint8_t _numStructElems, 171 uint8_t _numRegs, uint8_t _step) 172 : MicroOp(mnem, machInst, __opClass), dest(_dest), op1(_op1), 173 eSize(_eSize), dataSize(_dataSize), numStructElems(_numStructElems), 174 numRegs(_numRegs), step(_step) 175 { 176 } 177}; 178 179class MicroNeonMixLaneOp64 : public MicroOp 180{ 181 protected: 182 RegIndex dest, op1; 183 uint8_t eSize, dataSize, numStructElems, lane, step; 184 bool replicate; 185 186 MicroNeonMixLaneOp64(const char *mnem, ExtMachInst machInst, 187 OpClass __opClass, RegIndex _dest, RegIndex _op1, 188 uint8_t _eSize, uint8_t _dataSize, 189 uint8_t _numStructElems, uint8_t _lane, uint8_t _step, 190 bool _replicate = false) 191 : MicroOp(mnem, machInst, __opClass), dest(_dest), op1(_op1), 192 eSize(_eSize), dataSize(_dataSize), numStructElems(_numStructElems), 193 lane(_lane), step(_step), replicate(_replicate) 194 { 195 } 196}; 197 198/** 199 * Base classes for microcoded AArch64 NEON memory instructions. 200 */ 201class VldMultOp64 : public PredMacroOp 202{ 203 protected: 204 uint8_t eSize, dataSize, numStructElems, numRegs; 205 bool wb; 206 207 VldMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, 208 RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, 209 uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs, 210 bool wb); 211}; 212 213class VstMultOp64 : public PredMacroOp 214{ 215 protected: 216 uint8_t eSize, dataSize, numStructElems, numRegs; 217 bool wb; 218 219 VstMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, 220 RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, 221 uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs, 222 bool wb); 223}; 224 225class VldSingleOp64 : public PredMacroOp 226{ 227 protected: 228 uint8_t eSize, dataSize, numStructElems, index; 229 bool wb, replicate; 230 231 VldSingleOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, 232 RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, 233 uint8_t dataSize, uint8_t numStructElems, uint8_t index, 234 bool wb, bool replicate = false); 235}; 236 237class VstSingleOp64 : public PredMacroOp 238{ 239 protected: 240 uint8_t eSize, dataSize, numStructElems, index; 241 bool wb, replicate; 242 243 VstSingleOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, 244 RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, 245 uint8_t dataSize, uint8_t numStructElems, uint8_t index, 246 bool wb, bool replicate = false); 247}; 248 249/**
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139 * Microops of the form 140 * PC = IntRegA 141 * CPSR = IntRegB 142 */ 143class MicroSetPCCPSR : public MicroOp 144{ 145 protected: 146 IntRegIndex ura, urb, urc; 147 148 MicroSetPCCPSR(const char *mnem, ExtMachInst machInst, OpClass __opClass, 149 IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc) 150 : MicroOp(mnem, machInst, __opClass), 151 ura(_ura), urb(_urb), urc(_urc) 152 { 153 } 154 155 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 156}; 157 158/** 159 * Microops of the form IntRegA = IntRegB 160 */ 161class MicroIntMov : public MicroOp 162{ 163 protected: 164 RegIndex ura, urb; 165 166 MicroIntMov(const char *mnem, ExtMachInst machInst, OpClass __opClass, 167 RegIndex _ura, RegIndex _urb) 168 : MicroOp(mnem, machInst, __opClass), 169 ura(_ura), urb(_urb) 170 { 171 } 172 173 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 174}; 175 176/** 177 * Microops of the form IntRegA = IntRegB op Imm 178 */ 179class MicroIntImmOp : public MicroOp 180{ 181 protected: 182 RegIndex ura, urb;
| 250 * Microops of the form 251 * PC = IntRegA 252 * CPSR = IntRegB 253 */ 254class MicroSetPCCPSR : public MicroOp 255{ 256 protected: 257 IntRegIndex ura, urb, urc; 258 259 MicroSetPCCPSR(const char *mnem, ExtMachInst machInst, OpClass __opClass, 260 IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc) 261 : MicroOp(mnem, machInst, __opClass), 262 ura(_ura), urb(_urb), urc(_urc) 263 { 264 } 265 266 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 267}; 268 269/** 270 * Microops of the form IntRegA = IntRegB 271 */ 272class MicroIntMov : public MicroOp 273{ 274 protected: 275 RegIndex ura, urb; 276 277 MicroIntMov(const char *mnem, ExtMachInst machInst, OpClass __opClass, 278 RegIndex _ura, RegIndex _urb) 279 : MicroOp(mnem, machInst, __opClass), 280 ura(_ura), urb(_urb) 281 { 282 } 283 284 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 285}; 286 287/** 288 * Microops of the form IntRegA = IntRegB op Imm 289 */ 290class MicroIntImmOp : public MicroOp 291{ 292 protected: 293 RegIndex ura, urb;
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183 uint32_t imm;
| 294 int32_t imm;
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184 185 MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
| 295 296 MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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186 RegIndex _ura, RegIndex _urb, uint32_t _imm)
| 297 RegIndex _ura, RegIndex _urb, int32_t _imm)
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187 : MicroOp(mnem, machInst, __opClass), 188 ura(_ura), urb(_urb), imm(_imm) 189 { 190 } 191 192 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 193}; 194
| 298 : MicroOp(mnem, machInst, __opClass), 299 ura(_ura), urb(_urb), imm(_imm) 300 { 301 } 302 303 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 304}; 305
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| 306class MicroIntImmXOp : public MicroOpX 307{ 308 protected: 309 RegIndex ura, urb; 310 int64_t imm; 311 312 MicroIntImmXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 313 RegIndex _ura, RegIndex _urb, int64_t _imm) 314 : MicroOpX(mnem, machInst, __opClass), 315 ura(_ura), urb(_urb), imm(_imm) 316 { 317 } 318 319 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 320}; 321
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195/** 196 * Microops of the form IntRegA = IntRegB op IntRegC 197 */ 198class MicroIntOp : public MicroOp 199{ 200 protected: 201 RegIndex ura, urb, urc; 202 203 MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 204 RegIndex _ura, RegIndex _urb, RegIndex _urc) 205 : MicroOp(mnem, machInst, __opClass), 206 ura(_ura), urb(_urb), urc(_urc) 207 { 208 } 209 210 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 211}; 212
| 322/** 323 * Microops of the form IntRegA = IntRegB op IntRegC 324 */ 325class MicroIntOp : public MicroOp 326{ 327 protected: 328 RegIndex ura, urb, urc; 329 330 MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 331 RegIndex _ura, RegIndex _urb, RegIndex _urc) 332 : MicroOp(mnem, machInst, __opClass), 333 ura(_ura), urb(_urb), urc(_urc) 334 { 335 } 336 337 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 338}; 339
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| 340class MicroIntRegXOp : public MicroOp 341{ 342 protected: 343 RegIndex ura, urb, urc; 344 ArmExtendType type; 345 uint32_t shiftAmt; 346 347 MicroIntRegXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 348 RegIndex _ura, RegIndex _urb, RegIndex _urc, 349 ArmExtendType _type, uint32_t _shiftAmt) 350 : MicroOp(mnem, machInst, __opClass), 351 ura(_ura), urb(_urb), urc(_urc), 352 type(_type), shiftAmt(_shiftAmt) 353 { 354 } 355 356 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 357}; 358
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213/** 214 * Microops of the form IntRegA = IntRegB op shifted IntRegC 215 */ 216class MicroIntRegOp : public MicroOp 217{ 218 protected: 219 RegIndex ura, urb, urc; 220 int32_t shiftAmt; 221 ArmShiftType shiftType; 222 223 MicroIntRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 224 RegIndex _ura, RegIndex _urb, RegIndex _urc, 225 int32_t _shiftAmt, ArmShiftType _shiftType) 226 : MicroOp(mnem, machInst, __opClass), 227 ura(_ura), urb(_urb), urc(_urc), 228 shiftAmt(_shiftAmt), shiftType(_shiftType) 229 { 230 } 231}; 232 233/** 234 * Memory microops which use IntReg + Imm addressing 235 */ 236class MicroMemOp : public MicroIntImmOp 237{ 238 protected: 239 bool up; 240 unsigned memAccessFlags; 241 242 MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 243 RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm) 244 : MicroIntImmOp(mnem, machInst, __opClass, _ura, _urb, _imm), 245 up(_up), memAccessFlags(TLB::MustBeOne | TLB::AlignWord) 246 { 247 } 248 249 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 250}; 251 252/** 253 * Base class for microcoded integer memory instructions. 254 */ 255class MacroMemOp : public PredMacroOp 256{ 257 protected: 258 MacroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 259 IntRegIndex rn, bool index, bool up, bool user, 260 bool writeback, bool load, uint32_t reglist); 261}; 262 263/**
| 359/** 360 * Microops of the form IntRegA = IntRegB op shifted IntRegC 361 */ 362class MicroIntRegOp : public MicroOp 363{ 364 protected: 365 RegIndex ura, urb, urc; 366 int32_t shiftAmt; 367 ArmShiftType shiftType; 368 369 MicroIntRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 370 RegIndex _ura, RegIndex _urb, RegIndex _urc, 371 int32_t _shiftAmt, ArmShiftType _shiftType) 372 : MicroOp(mnem, machInst, __opClass), 373 ura(_ura), urb(_urb), urc(_urc), 374 shiftAmt(_shiftAmt), shiftType(_shiftType) 375 { 376 } 377}; 378 379/** 380 * Memory microops which use IntReg + Imm addressing 381 */ 382class MicroMemOp : public MicroIntImmOp 383{ 384 protected: 385 bool up; 386 unsigned memAccessFlags; 387 388 MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 389 RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm) 390 : MicroIntImmOp(mnem, machInst, __opClass, _ura, _urb, _imm), 391 up(_up), memAccessFlags(TLB::MustBeOne | TLB::AlignWord) 392 { 393 } 394 395 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 396}; 397 398/** 399 * Base class for microcoded integer memory instructions. 400 */ 401class MacroMemOp : public PredMacroOp 402{ 403 protected: 404 MacroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 405 IntRegIndex rn, bool index, bool up, bool user, 406 bool writeback, bool load, uint32_t reglist); 407}; 408 409/**
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| 410 * Base class for pair load/store instructions. 411 */ 412class PairMemOp : public PredMacroOp 413{ 414 public: 415 enum AddrMode { 416 AddrMd_Offset, 417 AddrMd_PreIndex, 418 AddrMd_PostIndex 419 }; 420 421 protected: 422 PairMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 423 uint32_t size, bool fp, bool load, bool noAlloc, bool signExt, 424 bool exclusive, bool acrel, int64_t imm, AddrMode mode, 425 IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2); 426}; 427 428class BigFpMemImmOp : public PredMacroOp 429{ 430 protected: 431 BigFpMemImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 432 bool load, IntRegIndex dest, IntRegIndex base, int64_t imm); 433}; 434 435class BigFpMemPostOp : public PredMacroOp 436{ 437 protected: 438 BigFpMemPostOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 439 bool load, IntRegIndex dest, IntRegIndex base, int64_t imm); 440}; 441 442class BigFpMemPreOp : public PredMacroOp 443{ 444 protected: 445 BigFpMemPreOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 446 bool load, IntRegIndex dest, IntRegIndex base, int64_t imm); 447}; 448 449class BigFpMemRegOp : public PredMacroOp 450{ 451 protected: 452 BigFpMemRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 453 bool load, IntRegIndex dest, IntRegIndex base, 454 IntRegIndex offset, ArmExtendType type, int64_t imm); 455}; 456 457class BigFpMemLitOp : public PredMacroOp 458{ 459 protected: 460 BigFpMemLitOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 461 IntRegIndex dest, int64_t imm); 462}; 463 464/**
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264 * Base classes for microcoded integer memory instructions. 265 */ 266class VldMultOp : public PredMacroOp 267{ 268 protected: 269 VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 270 unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, 271 unsigned inc, uint32_t size, uint32_t align, RegIndex rm); 272}; 273 274class VldSingleOp : public PredMacroOp 275{ 276 protected: 277 VldSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 278 bool all, unsigned elems, RegIndex rn, RegIndex vd, 279 unsigned regs, unsigned inc, uint32_t size, 280 uint32_t align, RegIndex rm, unsigned lane); 281}; 282 283/** 284 * Base class for microcoded integer memory instructions. 285 */ 286class VstMultOp : public PredMacroOp 287{ 288 protected: 289 VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 290 unsigned width, RegIndex rn, RegIndex vd, unsigned regs, 291 unsigned inc, uint32_t size, uint32_t align, RegIndex rm); 292}; 293 294class VstSingleOp : public PredMacroOp 295{ 296 protected: 297 VstSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 298 bool all, unsigned elems, RegIndex rn, RegIndex vd, 299 unsigned regs, unsigned inc, uint32_t size, 300 uint32_t align, RegIndex rm, unsigned lane); 301}; 302 303/** 304 * Base class for microcoded floating point memory instructions. 305 */ 306class MacroVFPMemOp : public PredMacroOp 307{ 308 protected: 309 MacroVFPMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 310 IntRegIndex rn, RegIndex vd, bool single, bool up, 311 bool writeback, bool load, uint32_t offset); 312}; 313 314} 315 316#endif //__ARCH_ARM_INSTS_MACROMEM_HH__
| 465 * Base classes for microcoded integer memory instructions. 466 */ 467class VldMultOp : public PredMacroOp 468{ 469 protected: 470 VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 471 unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, 472 unsigned inc, uint32_t size, uint32_t align, RegIndex rm); 473}; 474 475class VldSingleOp : public PredMacroOp 476{ 477 protected: 478 VldSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 479 bool all, unsigned elems, RegIndex rn, RegIndex vd, 480 unsigned regs, unsigned inc, uint32_t size, 481 uint32_t align, RegIndex rm, unsigned lane); 482}; 483 484/** 485 * Base class for microcoded integer memory instructions. 486 */ 487class VstMultOp : public PredMacroOp 488{ 489 protected: 490 VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 491 unsigned width, RegIndex rn, RegIndex vd, unsigned regs, 492 unsigned inc, uint32_t size, uint32_t align, RegIndex rm); 493}; 494 495class VstSingleOp : public PredMacroOp 496{ 497 protected: 498 VstSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 499 bool all, unsigned elems, RegIndex rn, RegIndex vd, 500 unsigned regs, unsigned inc, uint32_t size, 501 uint32_t align, RegIndex rm, unsigned lane); 502}; 503 504/** 505 * Base class for microcoded floating point memory instructions. 506 */ 507class MacroVFPMemOp : public PredMacroOp 508{ 509 protected: 510 MacroVFPMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 511 IntRegIndex rn, RegIndex vd, bool single, bool up, 512 bool writeback, bool load, uint32_t offset); 513}; 514 515} 516 517#endif //__ARCH_ARM_INSTS_MACROMEM_HH__
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