1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42#ifndef __ARCH_ARM_MACROMEM_HH__ 43#define __ARCH_ARM_MACROMEM_HH__ 44 45#include "arch/arm/insts/pred_inst.hh" 46#include "arch/arm/tlb.hh" 47 48namespace ArmISA 49{ 50 51static inline unsigned int 52number_of_ones(int32_t val) 53{ 54 uint32_t ones = 0; 55 for (int i = 0; i < 32; i++ ) 56 { 57 if ( val & (1<<i) ) 58 ones++; 59 } 60 return ones; 61} 62 63/** 64 * Base class for Memory microops 65 */ 66class MicroOp : public PredOp 67{ 68 protected: 69 MicroOp(const char *mnem, ExtMachInst machInst, OpClass __opClass) 70 : PredOp(mnem, machInst, __opClass) 71 { 72 } 73 74 public: 75 void 76 setDelayedCommit() 77 { 78 flags[IsDelayedCommit] = true; 79 } 80}; 81 82/** 83 * Microops for Neon loads/stores 84 */ 85class MicroNeonMemOp : public MicroOp 86{ 87 protected: 88 RegIndex dest, ura; 89 uint32_t imm; 90 unsigned memAccessFlags; 91 92 MicroNeonMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 93 RegIndex _dest, RegIndex _ura, uint32_t _imm) 94 : MicroOp(mnem, machInst, __opClass), 95 dest(_dest), ura(_ura), imm(_imm), 96 memAccessFlags(TLB::MustBeOne) 97 { 98 } 99}; 100 101/** 102 * Microops for Neon load/store (de)interleaving 103 */ 104class MicroNeonMixOp : public MicroOp 105{ 106 protected: 107 RegIndex dest, op1; 108 uint32_t step; 109 110 MicroNeonMixOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 111 RegIndex _dest, RegIndex _op1, uint32_t _step) 112 : MicroOp(mnem, machInst, __opClass), 113 dest(_dest), op1(_op1), step(_step) 114 { 115 } 116}; 117 118class MicroNeonMixLaneOp : public MicroNeonMixOp 119{ 120 protected: 121 unsigned lane; 122 123 MicroNeonMixLaneOp(const char *mnem, ExtMachInst machInst, 124 OpClass __opClass, RegIndex _dest, RegIndex _op1, 125 uint32_t _step, unsigned _lane) 126 : MicroNeonMixOp(mnem, machInst, __opClass, _dest, _op1, _step), 127 lane(_lane) 128 { 129 } 130};
| 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42#ifndef __ARCH_ARM_MACROMEM_HH__ 43#define __ARCH_ARM_MACROMEM_HH__ 44 45#include "arch/arm/insts/pred_inst.hh" 46#include "arch/arm/tlb.hh" 47 48namespace ArmISA 49{ 50 51static inline unsigned int 52number_of_ones(int32_t val) 53{ 54 uint32_t ones = 0; 55 for (int i = 0; i < 32; i++ ) 56 { 57 if ( val & (1<<i) ) 58 ones++; 59 } 60 return ones; 61} 62 63/** 64 * Base class for Memory microops 65 */ 66class MicroOp : public PredOp 67{ 68 protected: 69 MicroOp(const char *mnem, ExtMachInst machInst, OpClass __opClass) 70 : PredOp(mnem, machInst, __opClass) 71 { 72 } 73 74 public: 75 void 76 setDelayedCommit() 77 { 78 flags[IsDelayedCommit] = true; 79 } 80}; 81 82/** 83 * Microops for Neon loads/stores 84 */ 85class MicroNeonMemOp : public MicroOp 86{ 87 protected: 88 RegIndex dest, ura; 89 uint32_t imm; 90 unsigned memAccessFlags; 91 92 MicroNeonMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 93 RegIndex _dest, RegIndex _ura, uint32_t _imm) 94 : MicroOp(mnem, machInst, __opClass), 95 dest(_dest), ura(_ura), imm(_imm), 96 memAccessFlags(TLB::MustBeOne) 97 { 98 } 99}; 100 101/** 102 * Microops for Neon load/store (de)interleaving 103 */ 104class MicroNeonMixOp : public MicroOp 105{ 106 protected: 107 RegIndex dest, op1; 108 uint32_t step; 109 110 MicroNeonMixOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 111 RegIndex _dest, RegIndex _op1, uint32_t _step) 112 : MicroOp(mnem, machInst, __opClass), 113 dest(_dest), op1(_op1), step(_step) 114 { 115 } 116}; 117 118class MicroNeonMixLaneOp : public MicroNeonMixOp 119{ 120 protected: 121 unsigned lane; 122 123 MicroNeonMixLaneOp(const char *mnem, ExtMachInst machInst, 124 OpClass __opClass, RegIndex _dest, RegIndex _op1, 125 uint32_t _step, unsigned _lane) 126 : MicroNeonMixOp(mnem, machInst, __opClass, _dest, _op1, _step), 127 lane(_lane) 128 { 129 } 130};
|
| 131/** 132 * Microops of the form IntRegA = IntRegB 133 */ 134class MicroIntMov : public MicroOp 135{ 136 protected: 137 RegIndex ura, urb;
|
131
| 138
|
| 139 MicroIntMov(const char *mnem, ExtMachInst machInst, OpClass __opClass, 140 RegIndex _ura, RegIndex _urb) 141 : MicroOp(mnem, machInst, __opClass), 142 ura(_ura), urb(_urb) 143 { 144 } 145 146 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 147}; 148
|
132/** 133 * Microops of the form IntRegA = IntRegB op Imm 134 */ 135class MicroIntImmOp : public MicroOp 136{ 137 protected: 138 RegIndex ura, urb;
| 149/** 150 * Microops of the form IntRegA = IntRegB op Imm 151 */ 152class MicroIntImmOp : public MicroOp 153{ 154 protected: 155 RegIndex ura, urb;
|
139 uint8_t imm;
| 156 uint32_t imm;
|
140 141 MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
| 157 158 MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
|
142 RegIndex _ura, RegIndex _urb, uint8_t _imm)
| 159 RegIndex _ura, RegIndex _urb, uint32_t _imm)
|
143 : MicroOp(mnem, machInst, __opClass), 144 ura(_ura), urb(_urb), imm(_imm) 145 { 146 } 147 148 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 149}; 150 151/** 152 * Microops of the form IntRegA = IntRegB op IntRegC 153 */ 154class MicroIntOp : public MicroOp 155{ 156 protected: 157 RegIndex ura, urb, urc; 158 159 MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 160 RegIndex _ura, RegIndex _urb, RegIndex _urc) 161 : MicroOp(mnem, machInst, __opClass), 162 ura(_ura), urb(_urb), urc(_urc) 163 { 164 } 165 166 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 167}; 168 169/**
| 160 : MicroOp(mnem, machInst, __opClass), 161 ura(_ura), urb(_urb), imm(_imm) 162 { 163 } 164 165 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 166}; 167 168/** 169 * Microops of the form IntRegA = IntRegB op IntRegC 170 */ 171class MicroIntOp : public MicroOp 172{ 173 protected: 174 RegIndex ura, urb, urc; 175 176 MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 177 RegIndex _ura, RegIndex _urb, RegIndex _urc) 178 : MicroOp(mnem, machInst, __opClass), 179 ura(_ura), urb(_urb), urc(_urc) 180 { 181 } 182 183 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 184}; 185 186/**
|
| 187 * Microops of the form IntRegA = IntRegB op shifted IntRegC 188 */ 189class MicroIntRegOp : public MicroOp 190{ 191 protected: 192 RegIndex ura, urb, urc; 193 int32_t shiftAmt; 194 ArmShiftType shiftType; 195 196 MicroIntRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 197 RegIndex _ura, RegIndex _urb, RegIndex _urc, 198 int32_t _shiftAmt, ArmShiftType _shiftType) 199 : MicroOp(mnem, machInst, __opClass), 200 ura(_ura), urb(_urb), urc(_urc), 201 shiftAmt(_shiftAmt), shiftType(_shiftType) 202 { 203 } 204}; 205 206/**
|
170 * Memory microops which use IntReg + Imm addressing 171 */ 172class MicroMemOp : public MicroIntImmOp 173{ 174 protected: 175 bool up; 176 unsigned memAccessFlags; 177 178 MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 179 RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm) 180 : MicroIntImmOp(mnem, machInst, __opClass, _ura, _urb, _imm), 181 up(_up), memAccessFlags(TLB::MustBeOne | TLB::AlignWord) 182 { 183 } 184 185 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 186}; 187 188/** 189 * Base class for microcoded integer memory instructions. 190 */ 191class MacroMemOp : public PredMacroOp 192{ 193 protected: 194 MacroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 195 IntRegIndex rn, bool index, bool up, bool user, 196 bool writeback, bool load, uint32_t reglist); 197}; 198 199/** 200 * Base classes for microcoded integer memory instructions. 201 */ 202class VldMultOp : public PredMacroOp 203{ 204 protected: 205 VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 206 unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, 207 unsigned inc, uint32_t size, uint32_t align, RegIndex rm); 208}; 209 210class VldSingleOp : public PredMacroOp 211{ 212 protected: 213 VldSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 214 bool all, unsigned elems, RegIndex rn, RegIndex vd, 215 unsigned regs, unsigned inc, uint32_t size, 216 uint32_t align, RegIndex rm, unsigned lane); 217}; 218 219/** 220 * Base class for microcoded integer memory instructions. 221 */ 222class VstMultOp : public PredMacroOp 223{ 224 protected: 225 VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 226 unsigned width, RegIndex rn, RegIndex vd, unsigned regs, 227 unsigned inc, uint32_t size, uint32_t align, RegIndex rm); 228}; 229 230class VstSingleOp : public PredMacroOp 231{ 232 protected: 233 VstSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 234 bool all, unsigned elems, RegIndex rn, RegIndex vd, 235 unsigned regs, unsigned inc, uint32_t size, 236 uint32_t align, RegIndex rm, unsigned lane); 237}; 238 239/** 240 * Base class for microcoded floating point memory instructions. 241 */ 242class MacroVFPMemOp : public PredMacroOp 243{ 244 protected: 245 MacroVFPMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 246 IntRegIndex rn, RegIndex vd, bool single, bool up, 247 bool writeback, bool load, uint32_t offset); 248}; 249 250} 251 252#endif //__ARCH_ARM_INSTS_MACROMEM_HH__
| 207 * Memory microops which use IntReg + Imm addressing 208 */ 209class MicroMemOp : public MicroIntImmOp 210{ 211 protected: 212 bool up; 213 unsigned memAccessFlags; 214 215 MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 216 RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm) 217 : MicroIntImmOp(mnem, machInst, __opClass, _ura, _urb, _imm), 218 up(_up), memAccessFlags(TLB::MustBeOne | TLB::AlignWord) 219 { 220 } 221 222 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 223}; 224 225/** 226 * Base class for microcoded integer memory instructions. 227 */ 228class MacroMemOp : public PredMacroOp 229{ 230 protected: 231 MacroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 232 IntRegIndex rn, bool index, bool up, bool user, 233 bool writeback, bool load, uint32_t reglist); 234}; 235 236/** 237 * Base classes for microcoded integer memory instructions. 238 */ 239class VldMultOp : public PredMacroOp 240{ 241 protected: 242 VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 243 unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, 244 unsigned inc, uint32_t size, uint32_t align, RegIndex rm); 245}; 246 247class VldSingleOp : public PredMacroOp 248{ 249 protected: 250 VldSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 251 bool all, unsigned elems, RegIndex rn, RegIndex vd, 252 unsigned regs, unsigned inc, uint32_t size, 253 uint32_t align, RegIndex rm, unsigned lane); 254}; 255 256/** 257 * Base class for microcoded integer memory instructions. 258 */ 259class VstMultOp : public PredMacroOp 260{ 261 protected: 262 VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 263 unsigned width, RegIndex rn, RegIndex vd, unsigned regs, 264 unsigned inc, uint32_t size, uint32_t align, RegIndex rm); 265}; 266 267class VstSingleOp : public PredMacroOp 268{ 269 protected: 270 VstSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 271 bool all, unsigned elems, RegIndex rn, RegIndex vd, 272 unsigned regs, unsigned inc, uint32_t size, 273 uint32_t align, RegIndex rm, unsigned lane); 274}; 275 276/** 277 * Base class for microcoded floating point memory instructions. 278 */ 279class MacroVFPMemOp : public PredMacroOp 280{ 281 protected: 282 MacroVFPMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 283 IntRegIndex rn, RegIndex vd, bool single, bool up, 284 bool writeback, bool load, uint32_t offset); 285}; 286 287} 288 289#endif //__ARCH_ARM_INSTS_MACROMEM_HH__
|