macromem.hh (7130:12d7f945261f) macromem.hh (7134:60fe8a00b36e)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_MACROMEM_HH__
43#define __ARCH_ARM_MACROMEM_HH__
44
45#include "arch/arm/insts/pred_inst.hh"
46
47namespace ArmISA
48{
49
50static inline unsigned int
51number_of_ones(int32_t val)
52{
53 uint32_t ones = 0;
54 for (int i = 0; i < 32; i++ )
55 {
56 if ( val & (1<<i) )
57 ones++;
58 }
59 return ones;
60}
61
62/**
63 * Microops of the form IntRegA = IntRegB op Imm
64 */
65class MicroIntOp : public PredOp
66{
67 protected:
68 RegIndex ura, urb;
69 uint8_t imm;
70
71 MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
72 RegIndex _ura, RegIndex _urb, uint8_t _imm)
73 : PredOp(mnem, machInst, __opClass),
74 ura(_ura), urb(_urb), imm(_imm)
75 {
76 }
77};
78
79/**
80 * Memory microops which use IntReg + Imm addressing
81 */
82class MicroMemOp : public MicroIntOp
83{
84 protected:
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_MACROMEM_HH__
43#define __ARCH_ARM_MACROMEM_HH__
44
45#include "arch/arm/insts/pred_inst.hh"
46
47namespace ArmISA
48{
49
50static inline unsigned int
51number_of_ones(int32_t val)
52{
53 uint32_t ones = 0;
54 for (int i = 0; i < 32; i++ )
55 {
56 if ( val & (1<<i) )
57 ones++;
58 }
59 return ones;
60}
61
62/**
63 * Microops of the form IntRegA = IntRegB op Imm
64 */
65class MicroIntOp : public PredOp
66{
67 protected:
68 RegIndex ura, urb;
69 uint8_t imm;
70
71 MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
72 RegIndex _ura, RegIndex _urb, uint8_t _imm)
73 : PredOp(mnem, machInst, __opClass),
74 ura(_ura), urb(_urb), imm(_imm)
75 {
76 }
77};
78
79/**
80 * Memory microops which use IntReg + Imm addressing
81 */
82class MicroMemOp : public MicroIntOp
83{
84 protected:
85 bool up;
85 unsigned memAccessFlags;
86
87 MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
86 unsigned memAccessFlags;
87
88 MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
88 RegIndex _ura, RegIndex _urb, uint8_t _imm)
89 RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm)
89 : MicroIntOp(mnem, machInst, __opClass, _ura, _urb, _imm),
90 : MicroIntOp(mnem, machInst, __opClass, _ura, _urb, _imm),
90 memAccessFlags(0)
91 up(_up), memAccessFlags(0)
91 {
92 }
93};
94
92 {
93 }
94};
95
95/**
96 * Arm Macro Memory operations like LDM/STM
97 */
98class ArmMacroMemoryOp : public PredMacroOp
99{
100 protected:
101 /// Memory request flags. See mem_req_base.hh.
102 unsigned memAccessFlags;
103
104 uint32_t reglist;
105 uint32_t ones;
106
107 ArmMacroMemoryOp(const char *mnem, ExtMachInst _machInst,
108 OpClass __opClass)
109 : PredMacroOp(mnem, _machInst, __opClass), memAccessFlags(0),
110 reglist(machInst.regList), ones(0)
111 {
112 ones = number_of_ones(reglist);
113 numMicroops = ones + machInst.puswl.writeback + 1;
114 // Remember that writeback adds a uop
115 microOps = new StaticInstPtr[numMicroops];
116 }
117};
118}
119
120#endif //__ARCH_ARM_INSTS_MACROMEM_HH__
96}
97
98#endif //__ARCH_ARM_INSTS_MACROMEM_HH__