1/* Copyright (c) 2007-2008 The Florida State University
2 * All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met: redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer;
8 * redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in the
10 * documentation and/or other materials provided with the distribution;
11 * neither the name of the copyright holders nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * Authors: Stephen Hines
28 */
29#ifndef __ARCH_ARM_MACROMEM_HH__
30#define __ARCH_ARM_MACROMEM_HH__
31
32#include "arch/arm/insts/pred_inst.hh"
33
34namespace ArmISA
35{
36
37static inline unsigned int
38number_of_ones(int32_t val)
39{
40 uint32_t ones = 0;
41 for (int i = 0; i < 32; i++ )
42 {
43 if ( val & (1<<i) )
44 ones++;
45 }
46 return ones;
47}
48
49/**
50 * Microops of the form IntRegA = IntRegB op Imm
51 */
52class MicroIntOp : public PredOp
53{
54 protected:
55 RegIndex ura, urb;
56 uint8_t imm;
57
58 MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
59 RegIndex _ura, RegIndex _urb, uint8_t _imm)
60 : PredOp(mnem, machInst, __opClass),
61 ura(_ura), urb(_urb), imm(_imm)
62 {
63 }
64};
65
66/**
| 1/* Copyright (c) 2007-2008 The Florida State University
2 * All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met: redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer;
8 * redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in the
10 * documentation and/or other materials provided with the distribution;
11 * neither the name of the copyright holders nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * Authors: Stephen Hines
28 */
29#ifndef __ARCH_ARM_MACROMEM_HH__
30#define __ARCH_ARM_MACROMEM_HH__
31
32#include "arch/arm/insts/pred_inst.hh"
33
34namespace ArmISA
35{
36
37static inline unsigned int
38number_of_ones(int32_t val)
39{
40 uint32_t ones = 0;
41 for (int i = 0; i < 32; i++ )
42 {
43 if ( val & (1<<i) )
44 ones++;
45 }
46 return ones;
47}
48
49/**
50 * Microops of the form IntRegA = IntRegB op Imm
51 */
52class MicroIntOp : public PredOp
53{
54 protected:
55 RegIndex ura, urb;
56 uint8_t imm;
57
58 MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
59 RegIndex _ura, RegIndex _urb, uint8_t _imm)
60 : PredOp(mnem, machInst, __opClass),
61 ura(_ura), urb(_urb), imm(_imm)
62 {
63 }
64};
65
66/**
|
67 * Arm Macro Memory operations like LDM/STM
68 */
69class ArmMacroMemoryOp : public PredMacroOp
70{
71 protected:
72 /// Memory request flags. See mem_req_base.hh.
73 unsigned memAccessFlags;
74
75 uint32_t reglist;
76 uint32_t ones;
77 uint32_t puswl,
78 prepost,
79 up,
80 psruser,
81 writeback,
82 loadop;
83
84 ArmMacroMemoryOp(const char *mnem, ExtMachInst _machInst,
85 OpClass __opClass)
86 : PredMacroOp(mnem, _machInst, __opClass),
87 memAccessFlags(0),
88 reglist(machInst.regList), ones(0),
89 puswl(machInst.puswl),
90 prepost(machInst.puswl.prepost),
91 up(machInst.puswl.up),
92 psruser(machInst.puswl.psruser),
93 writeback(machInst.puswl.writeback),
94 loadop(machInst.puswl.loadOp)
95 {
96 ones = number_of_ones(reglist);
97 numMicroops = ones + writeback + 1;
98 // Remember that writeback adds a uop
99 microOps = new StaticInstPtr[numMicroops];
100 }
101};
102
103/**
104 * Arm Macro FPA operations to fix ldfd and stfd instructions
105 */
106class ArmMacroFPAOp : public PredMacroOp
107{
108 protected:
109 uint32_t puswl,
110 prepost,
111 up,
112 psruser,
113 writeback,
114 loadop;
115 int32_t disp8;
116
117 ArmMacroFPAOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
118 : PredMacroOp(mnem, _machInst, __opClass),
119 puswl(machInst.puswl),
120 prepost(machInst.puswl.prepost),
121 up(machInst.puswl.up),
122 psruser(machInst.puswl.psruser),
123 writeback(machInst.puswl.writeback),
124 loadop(machInst.puswl.loadOp),
125 disp8(machInst.immed7_0 << 2)
126 {
127 numMicroops = 3 + writeback;
128 microOps = new StaticInstPtr[numMicroops];
129 }
130};
131
132/**
133 * Arm Macro FM operations to fix lfm and sfm
134 */
135class ArmMacroFMOp : public PredMacroOp
136{
137 protected:
138 uint32_t punwl,
139 prepost,
140 up,
141 n1bit,
142 writeback,
143 loadop,
144 n0bit,
145 count;
146 int32_t disp8;
147
148 ArmMacroFMOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
149 : PredMacroOp(mnem, _machInst, __opClass),
150 punwl(machInst.punwl),
151 prepost(machInst.puswl.prepost),
152 up(machInst.puswl.up),
153 n1bit(machInst.opcode22),
154 writeback(machInst.puswl.writeback),
155 loadop(machInst.puswl.loadOp),
156 n0bit(machInst.opcode15),
157 disp8(machInst.immed7_0 << 2)
158 {
159 // Transfer 1-4 registers based on n1 and n0 bits (with 00 repr. 4)
160 count = (n1bit << 1) | n0bit;
161 if (count == 0)
162 count = 4;
163 numMicroops = (3*count) + writeback;
164 microOps = new StaticInstPtr[numMicroops];
165 }
166};
167}
168
169#endif //__ARCH_ARM_INSTS_MACROMEM_HH__
| 83 * Arm Macro Memory operations like LDM/STM
84 */
85class ArmMacroMemoryOp : public PredMacroOp
86{
87 protected:
88 /// Memory request flags. See mem_req_base.hh.
89 unsigned memAccessFlags;
90
91 uint32_t reglist;
92 uint32_t ones;
93 uint32_t puswl,
94 prepost,
95 up,
96 psruser,
97 writeback,
98 loadop;
99
100 ArmMacroMemoryOp(const char *mnem, ExtMachInst _machInst,
101 OpClass __opClass)
102 : PredMacroOp(mnem, _machInst, __opClass),
103 memAccessFlags(0),
104 reglist(machInst.regList), ones(0),
105 puswl(machInst.puswl),
106 prepost(machInst.puswl.prepost),
107 up(machInst.puswl.up),
108 psruser(machInst.puswl.psruser),
109 writeback(machInst.puswl.writeback),
110 loadop(machInst.puswl.loadOp)
111 {
112 ones = number_of_ones(reglist);
113 numMicroops = ones + writeback + 1;
114 // Remember that writeback adds a uop
115 microOps = new StaticInstPtr[numMicroops];
116 }
117};
118
119/**
120 * Arm Macro FPA operations to fix ldfd and stfd instructions
121 */
122class ArmMacroFPAOp : public PredMacroOp
123{
124 protected:
125 uint32_t puswl,
126 prepost,
127 up,
128 psruser,
129 writeback,
130 loadop;
131 int32_t disp8;
132
133 ArmMacroFPAOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
134 : PredMacroOp(mnem, _machInst, __opClass),
135 puswl(machInst.puswl),
136 prepost(machInst.puswl.prepost),
137 up(machInst.puswl.up),
138 psruser(machInst.puswl.psruser),
139 writeback(machInst.puswl.writeback),
140 loadop(machInst.puswl.loadOp),
141 disp8(machInst.immed7_0 << 2)
142 {
143 numMicroops = 3 + writeback;
144 microOps = new StaticInstPtr[numMicroops];
145 }
146};
147
148/**
149 * Arm Macro FM operations to fix lfm and sfm
150 */
151class ArmMacroFMOp : public PredMacroOp
152{
153 protected:
154 uint32_t punwl,
155 prepost,
156 up,
157 n1bit,
158 writeback,
159 loadop,
160 n0bit,
161 count;
162 int32_t disp8;
163
164 ArmMacroFMOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
165 : PredMacroOp(mnem, _machInst, __opClass),
166 punwl(machInst.punwl),
167 prepost(machInst.puswl.prepost),
168 up(machInst.puswl.up),
169 n1bit(machInst.opcode22),
170 writeback(machInst.puswl.writeback),
171 loadop(machInst.puswl.loadOp),
172 n0bit(machInst.opcode15),
173 disp8(machInst.immed7_0 << 2)
174 {
175 // Transfer 1-4 registers based on n1 and n0 bits (with 00 repr. 4)
176 count = (n1bit << 1) | n0bit;
177 if (count == 0)
178 count = 4;
179 numMicroops = (3*count) + writeback;
180 microOps = new StaticInstPtr[numMicroops];
181 }
182};
183}
184
185#endif //__ARCH_ARM_INSTS_MACROMEM_HH__
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