1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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68 protected:
69 MicroOp(const char *mnem, ExtMachInst machInst, OpClass __opClass)
70 : PredOp(mnem, machInst, __opClass)
71 {
72 }
73
74 public:
75 void
76 advancePC(PCState &pcState) const
77 {
78 if (flags[IsLastMicroop]) {
79 pcState.uEnd();
80 } else if (flags[IsMicroop]) {
81 pcState.uAdvance();
82 } else {
83 pcState.advance();
84 }

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89{
90 protected:
91 MicroOpX(const char *mnem, ExtMachInst machInst, OpClass __opClass)
92 : ArmStaticInst(mnem, machInst, __opClass)
93 {}
94
95 public:
96 void
97 advancePC(PCState &pcState) const
98 {
99 if (flags[IsLastMicroop]) {
100 pcState.uEnd();
101 } else if (flags[IsMicroop]) {
102 pcState.uAdvance();
103 } else {
104 pcState.advance();
105 }

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258
259 MicroSetPCCPSR(const char *mnem, ExtMachInst machInst, OpClass __opClass,
260 IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc)
261 : MicroOp(mnem, machInst, __opClass),
262 ura(_ura), urb(_urb), urc(_urc)
263 {
264 }
265
266 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
267};
268
269/**
270 * Microops of the form IntRegA = IntRegB
271 */
272class MicroIntMov : public MicroOp
273{
274 protected:
275 RegIndex ura, urb;
276
277 MicroIntMov(const char *mnem, ExtMachInst machInst, OpClass __opClass,
278 RegIndex _ura, RegIndex _urb)
279 : MicroOp(mnem, machInst, __opClass),
280 ura(_ura), urb(_urb)
281 {
282 }
283
284 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
285};
286
287/**
288 * Microops of the form IntRegA = IntRegB op Imm
289 */
290class MicroIntImmOp : public MicroOp
291{
292 protected:
293 RegIndex ura, urb;
294 int32_t imm;
295
296 MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
297 RegIndex _ura, RegIndex _urb, int32_t _imm)
298 : MicroOp(mnem, machInst, __opClass),
299 ura(_ura), urb(_urb), imm(_imm)
300 {
301 }
302
303 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
304};
305
306class MicroIntImmXOp : public MicroOpX
307{
308 protected:
309 RegIndex ura, urb;
310 int64_t imm;
311
312 MicroIntImmXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
313 RegIndex _ura, RegIndex _urb, int64_t _imm)
314 : MicroOpX(mnem, machInst, __opClass),
315 ura(_ura), urb(_urb), imm(_imm)
316 {
317 }
318
319 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
320};
321
322/**
323 * Microops of the form IntRegA = IntRegB op IntRegC
324 */
325class MicroIntOp : public MicroOp
326{
327 protected:
328 RegIndex ura, urb, urc;
329
330 MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
331 RegIndex _ura, RegIndex _urb, RegIndex _urc)
332 : MicroOp(mnem, machInst, __opClass),
333 ura(_ura), urb(_urb), urc(_urc)
334 {
335 }
336
337 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
338};
339
340class MicroIntRegXOp : public MicroOp
341{
342 protected:
343 RegIndex ura, urb, urc;
344 ArmExtendType type;
345 uint32_t shiftAmt;
346
347 MicroIntRegXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
348 RegIndex _ura, RegIndex _urb, RegIndex _urc,
349 ArmExtendType _type, uint32_t _shiftAmt)
350 : MicroOp(mnem, machInst, __opClass),
351 ura(_ura), urb(_urb), urc(_urc),
352 type(_type), shiftAmt(_shiftAmt)
353 {
354 }
355
356 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
357};
358
359/**
360 * Microops of the form IntRegA = IntRegB op shifted IntRegC
361 */
362class MicroIntRegOp : public MicroOp
363{
364 protected:

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387
388 MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
389 RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm)
390 : MicroIntImmOp(mnem, machInst, __opClass, _ura, _urb, _imm),
391 up(_up), memAccessFlags(TLB::MustBeOne | TLB::AlignWord)
392 {
393 }
394
395 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
396};
397
398class MicroMemPairOp : public MicroOp
399{
400 protected:
401 RegIndex dest, dest2, urb;
402 bool up;
403 int32_t imm;
404 unsigned memAccessFlags;
405
406 MicroMemPairOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
407 RegIndex _dreg1, RegIndex _dreg2, RegIndex _base,
408 bool _up, uint8_t _imm)
409 : MicroOp(mnem, machInst, __opClass),
410 dest(_dreg1), dest2(_dreg2), urb(_base), up(_up), imm(_imm),
411 memAccessFlags(TLB::MustBeOne | TLB::AlignWord)
412 {
413 }
414
415 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
416};
417
418/**
419 * Base class for microcoded integer memory instructions.
420 */
421class MacroMemOp : public PredMacroOp
422{
423 protected:

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