macromem.cc (7639:8c09b7ff5b57) macromem.cc (7646:a444dbee8c07)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 171 unchanged lines hidden (view full) ---

180 size, machInst, rMid, rn, 0, align);
181 break;
182 default:
183 panic("Unrecognized number of registers %d.\n", regs);
184 }
185 if (wb) {
186 if (rm != 15 && rm != 13) {
187 microOps[uopIdx++] =
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 171 unchanged lines hidden (view full) ---

180 size, machInst, rMid, rn, 0, align);
181 break;
182 default:
183 panic("Unrecognized number of registers %d.\n", regs);
184 }
185 if (wb) {
186 if (rm != 15 && rm != 13) {
187 microOps[uopIdx++] =
188 new MicroAddUop(machInst, rn, rn, rm);
188 new MicroAddUop(machInst, rn, rn, rm, 0, ArmISA::LSL);
189 } else {
190 microOps[uopIdx++] =
191 new MicroAddiUop(machInst, rn, rn, regs * 8);
192 }
193 }
194 if (deinterleave) {
195 switch (elems) {
196 case 4:

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315 machInst, ufp0, rn, 0, align);
316 break;
317 default:
318 panic("Unrecognized load size %d.\n", regs);
319 }
320 if (wb) {
321 if (rm != 15 && rm != 13) {
322 microOps[uopIdx++] =
189 } else {
190 microOps[uopIdx++] =
191 new MicroAddiUop(machInst, rn, rn, regs * 8);
192 }
193 }
194 if (deinterleave) {
195 switch (elems) {
196 case 4:

--- 118 unchanged lines hidden (view full) ---

315 machInst, ufp0, rn, 0, align);
316 break;
317 default:
318 panic("Unrecognized load size %d.\n", regs);
319 }
320 if (wb) {
321 if (rm != 15 && rm != 13) {
322 microOps[uopIdx++] =
323 new MicroAddUop(machInst, rn, rn, rm);
323 new MicroAddUop(machInst, rn, rn, rm, 0, ArmISA::LSL);
324 } else {
325 microOps[uopIdx++] =
326 new MicroAddiUop(machInst, rn, rn, loadSize);
327 }
328 }
329 switch (elems) {
330 case 4:
331 assert(regs == 4);

--- 229 unchanged lines hidden (view full) ---

561 size, machInst, rMid, rn, 0, align);
562 break;
563 default:
564 panic("Unrecognized number of registers %d.\n", regs);
565 }
566 if (wb) {
567 if (rm != 15 && rm != 13) {
568 microOps[uopIdx++] =
324 } else {
325 microOps[uopIdx++] =
326 new MicroAddiUop(machInst, rn, rn, loadSize);
327 }
328 }
329 switch (elems) {
330 case 4:
331 assert(regs == 4);

--- 229 unchanged lines hidden (view full) ---

561 size, machInst, rMid, rn, 0, align);
562 break;
563 default:
564 panic("Unrecognized number of registers %d.\n", regs);
565 }
566 if (wb) {
567 if (rm != 15 && rm != 13) {
568 microOps[uopIdx++] =
569 new MicroAddUop(machInst, rn, rn, rm);
569 new MicroAddUop(machInst, rn, rn, rm, 0, ArmISA::LSL);
570 } else {
571 microOps[uopIdx++] =
572 new MicroAddiUop(machInst, rn, rn, regs * 8);
573 }
574 }
575 assert(uopIdx == numMicroops);
576
577 for (unsigned i = 0; i < numMicroops - 1; i++) {

--- 179 unchanged lines hidden (view full) ---

757 machInst, ufp0, rn, 0, align);
758 break;
759 default:
760 panic("Unrecognized store size %d.\n", regs);
761 }
762 if (wb) {
763 if (rm != 15 && rm != 13) {
764 microOps[uopIdx++] =
570 } else {
571 microOps[uopIdx++] =
572 new MicroAddiUop(machInst, rn, rn, regs * 8);
573 }
574 }
575 assert(uopIdx == numMicroops);
576
577 for (unsigned i = 0; i < numMicroops - 1; i++) {

--- 179 unchanged lines hidden (view full) ---

757 machInst, ufp0, rn, 0, align);
758 break;
759 default:
760 panic("Unrecognized store size %d.\n", regs);
761 }
762 if (wb) {
763 if (rm != 15 && rm != 13) {
764 microOps[uopIdx++] =
765 new MicroAddUop(machInst, rn, rn, rm);
765 new MicroAddUop(machInst, rn, rn, rm, 0, ArmISA::LSL);
766 } else {
767 microOps[uopIdx++] =
768 new MicroAddiUop(machInst, rn, rn, storeSize);
769 }
770 }
771 assert(uopIdx == numMicroops);
772
773 for (unsigned i = 0; i < numMicroops - 1; i++) {

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873 ss << ", ";
874 printReg(ss, urb);
875 ss << ", ";
876 ccprintf(ss, "#%d", imm);
877 return ss.str();
878}
879
880std::string
766 } else {
767 microOps[uopIdx++] =
768 new MicroAddiUop(machInst, rn, rn, storeSize);
769 }
770 }
771 assert(uopIdx == numMicroops);
772
773 for (unsigned i = 0; i < numMicroops - 1; i++) {

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873 ss << ", ";
874 printReg(ss, urb);
875 ss << ", ";
876 ccprintf(ss, "#%d", imm);
877 return ss.str();
878}
879
880std::string
881MicroIntMov::generateDisassembly(Addr pc, const SymbolTable *symtab) const
882{
883 std::stringstream ss;
884 printMnemonic(ss);
885 printReg(ss, ura);
886 ss << ", ";
887 printReg(ss, urb);
888 return ss.str();
889}
890
891std::string
881MicroIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
882{
883 std::stringstream ss;
884 printMnemonic(ss);
885 printReg(ss, ura);
886 ss << ", ";
887 printReg(ss, urb);
888 ss << ", ";

--- 19 unchanged lines hidden --- 		892MicroIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
893{
894 std::stringstream ss;
895 printMnemonic(ss);
896 printReg(ss, ura);
897 ss << ", ";
898 printReg(ss, urb);
899 ss << ", ";

--- 19 unchanged lines hidden ---