macromem.cc (10666:3c42be107634) macromem.cc (11321:02e930db812d)
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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140
141 if (up) addr += 8;
142 else addr -= 8;
143 mem_ops -= 2;
144 } else {
145 // 32-bit memory operation
146 // Find register for operation
147 unsigned reg_idx;
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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140
141 if (up) addr += 8;
142 else addr -= 8;
143 mem_ops -= 2;
144 } else {
145 // 32-bit memory operation
146 // Find register for operation
147 unsigned reg_idx;
148 while(!bits(regs, reg)) reg++;
148 while (!bits(regs, reg)) reg++;
149 replaceBits(regs, reg, 0);
150 reg_idx = force_user ? intRegInMode(MODE_USER, reg) : reg;
151
152 if (load) {
153 if (writeback && reg_idx == INTREG_PC) {
154 // If this instruction changes the PC and performs a
155 // writeback, ensure the pc load/branch is the last uop.
156 // Load into a temp reg here.

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1144 numMicroops += numMarshalMicroops;
1145
1146 microOps = new StaticInstPtr[numMicroops];
1147 unsigned uopIdx = 0;
1148 uint32_t memaccessFlags = TLB::MustBeOne | (TLB::ArmFlags) eSize |
1149 TLB::AllowUnaligned;
1150
1151 int i = 0;
149 replaceBits(regs, reg, 0);
150 reg_idx = force_user ? intRegInMode(MODE_USER, reg) : reg;
151
152 if (load) {
153 if (writeback && reg_idx == INTREG_PC) {
154 // If this instruction changes the PC and performs a
155 // writeback, ensure the pc load/branch is the last uop.
156 // Load into a temp reg here.

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1144 numMicroops += numMarshalMicroops;
1145
1146 microOps = new StaticInstPtr[numMicroops];
1147 unsigned uopIdx = 0;
1148 uint32_t memaccessFlags = TLB::MustBeOne | (TLB::ArmFlags) eSize |
1149 TLB::AllowUnaligned;
1150
1151 int i = 0;
1152 for(; i < numMemMicroops - 1; ++i) {
1152 for (; i < numMemMicroops - 1; ++i) {
1153 microOps[uopIdx++] = new MicroNeonLoad64(
1154 machInst, vx + (RegIndex) i, rnsp, 16 * i, memaccessFlags,
1155 baseIsSP, 16 /* accSize */, eSize);
1156 }
1157 microOps[uopIdx++] = new MicroNeonLoad64(
1158 machInst, vx + (RegIndex) i, rnsp, 16 * i, memaccessFlags, baseIsSP,
1159 residuum ? residuum : 16 /* accSize */, eSize);
1160

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1226 numMicroops += numMemMicroops;
1227
1228 int numMarshalMicroops = totNumBytes > 32 ? 2 : 1;
1229 numMicroops += numMarshalMicroops;
1230
1231 microOps = new StaticInstPtr[numMicroops];
1232 unsigned uopIdx = 0;
1233
1153 microOps[uopIdx++] = new MicroNeonLoad64(
1154 machInst, vx + (RegIndex) i, rnsp, 16 * i, memaccessFlags,
1155 baseIsSP, 16 /* accSize */, eSize);
1156 }
1157 microOps[uopIdx++] = new MicroNeonLoad64(
1158 machInst, vx + (RegIndex) i, rnsp, 16 * i, memaccessFlags, baseIsSP,
1159 residuum ? residuum : 16 /* accSize */, eSize);
1160

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1226 numMicroops += numMemMicroops;
1227
1228 int numMarshalMicroops = totNumBytes > 32 ? 2 : 1;
1229 numMicroops += numMarshalMicroops;
1230
1231 microOps = new StaticInstPtr[numMicroops];
1232 unsigned uopIdx = 0;
1233
1234 for(int i = 0; i < numMarshalMicroops; ++i) {
1234 for (int i = 0; i < numMarshalMicroops; ++i) {
1235 switch (numRegs) {
1236 case 1: microOps[uopIdx++] = new MicroIntNeon64_1Reg(
1237 machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
1238 numStructElems, 1, i /* step */);
1239 break;
1240 case 2: microOps[uopIdx++] = new MicroIntNeon64_2Reg(
1241 machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
1242 numStructElems, 2, i /* step */);

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1252 default: panic("Invalid number of registers");
1253 }
1254 }
1255
1256 uint32_t memaccessFlags = TLB::MustBeOne | (TLB::ArmFlags) eSize |
1257 TLB::AllowUnaligned;
1258
1259 int i = 0;
1235 switch (numRegs) {
1236 case 1: microOps[uopIdx++] = new MicroIntNeon64_1Reg(
1237 machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
1238 numStructElems, 1, i /* step */);
1239 break;
1240 case 2: microOps[uopIdx++] = new MicroIntNeon64_2Reg(
1241 machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
1242 numStructElems, 2, i /* step */);

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1252 default: panic("Invalid number of registers");
1253 }
1254 }
1255
1256 uint32_t memaccessFlags = TLB::MustBeOne | (TLB::ArmFlags) eSize |
1257 TLB::AllowUnaligned;
1258
1259 int i = 0;
1260 for(; i < numMemMicroops - 1; ++i) {
1260 for (; i < numMemMicroops - 1; ++i) {
1261 microOps[uopIdx++] = new MicroNeonStore64(
1262 machInst, vx + (RegIndex) i, rnsp, 16 * i, memaccessFlags,
1263 baseIsSP, 16 /* accSize */, eSize);
1264 }
1265 microOps[uopIdx++] = new MicroNeonStore64(
1266 machInst, vx + (RegIndex) i, rnsp, 16 * i, memaccessFlags, baseIsSP,
1267 residuum ? residuum : 16 /* accSize */, eSize);
1268

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1342 microOps[uopIdx++] = new MicroAddXERegUop(machInst, rnsp, rnsp, rm,
1343 UXTX, 0);
1344 } else {
1345 microOps[uopIdx++] = new MicroAddXiUop(machInst, rnsp, rnsp,
1346 totNumBytes);
1347 }
1348 }
1349
1261 microOps[uopIdx++] = new MicroNeonStore64(
1262 machInst, vx + (RegIndex) i, rnsp, 16 * i, memaccessFlags,
1263 baseIsSP, 16 /* accSize */, eSize);
1264 }
1265 microOps[uopIdx++] = new MicroNeonStore64(
1266 machInst, vx + (RegIndex) i, rnsp, 16 * i, memaccessFlags, baseIsSP,
1267 residuum ? residuum : 16 /* accSize */, eSize);
1268

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1342 microOps[uopIdx++] = new MicroAddXERegUop(machInst, rnsp, rnsp, rm,
1343 UXTX, 0);
1344 } else {
1345 microOps[uopIdx++] = new MicroAddXiUop(machInst, rnsp, rnsp,
1346 totNumBytes);
1347 }
1348 }
1349
1350 for(int i = 0; i < numMarshalMicroops; ++i) {
1350 for (int i = 0; i < numMarshalMicroops; ++i) {
1351 microOps[uopIdx++] = new MicroUnpackNeon64(
1352 machInst, vd + (RegIndex) (2 * i), vx, eSize, dataSize,
1353 numStructElems, index, i /* step */, replicate);
1354 }
1355
1356 assert(uopIdx == numMicroops);
1357
1358 for (int i = 0; i < numMicroops - 1; i++) {

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1389 numMicroops += numMemMicroops;
1390
1391 int numMarshalMicroops = totNumBytes > 32 ? 2 : 1;
1392 numMicroops += numMarshalMicroops;
1393
1394 microOps = new StaticInstPtr[numMicroops];
1395 unsigned uopIdx = 0;
1396
1351 microOps[uopIdx++] = new MicroUnpackNeon64(
1352 machInst, vd + (RegIndex) (2 * i), vx, eSize, dataSize,
1353 numStructElems, index, i /* step */, replicate);
1354 }
1355
1356 assert(uopIdx == numMicroops);
1357
1358 for (int i = 0; i < numMicroops - 1; i++) {

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1389 numMicroops += numMemMicroops;
1390
1391 int numMarshalMicroops = totNumBytes > 32 ? 2 : 1;
1392 numMicroops += numMarshalMicroops;
1393
1394 microOps = new StaticInstPtr[numMicroops];
1395 unsigned uopIdx = 0;
1396
1397 for(int i = 0; i < numMarshalMicroops; ++i) {
1397 for (int i = 0; i < numMarshalMicroops; ++i) {
1398 microOps[uopIdx++] = new MicroPackNeon64(
1399 machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
1400 numStructElems, index, i /* step */, replicate);
1401 }
1402
1403 uint32_t memaccessFlags = TLB::MustBeOne | (TLB::ArmFlags) eSize |
1404 TLB::AllowUnaligned;
1405
1406 int i = 0;
1398 microOps[uopIdx++] = new MicroPackNeon64(
1399 machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
1400 numStructElems, index, i /* step */, replicate);
1401 }
1402
1403 uint32_t memaccessFlags = TLB::MustBeOne | (TLB::ArmFlags) eSize |
1404 TLB::AllowUnaligned;
1405
1406 int i = 0;
1407 for(; i < numMemMicroops - 1; ++i) {
1407 for (; i < numMemMicroops - 1; ++i) {
1408 microOps[uopIdx++] = new MicroNeonStore64(
1409 machInst, vx + (RegIndex) i, rnsp, 16 * i, memaccessFlags,
1410 baseIsSP, 16 /* accsize */, eSize);
1411 }
1412 microOps[uopIdx++] = new MicroNeonStore64(
1413 machInst, vx + (RegIndex) i, rnsp, 16 * i, memaccessFlags, baseIsSP,
1414 residuum ? residuum : 16 /* accSize */, eSize);
1415

--- 212 unchanged lines hidden --- 		1408 microOps[uopIdx++] = new MicroNeonStore64(
1409 machInst, vx + (RegIndex) i, rnsp, 16 * i, memaccessFlags,
1410 baseIsSP, 16 /* accsize */, eSize);
1411 }
1412 microOps[uopIdx++] = new MicroNeonStore64(
1413 machInst, vx + (RegIndex) i, rnsp, 16 * i, memaccessFlags, baseIsSP,
1414 residuum ? residuum : 16 /* accSize */, eSize);
1415

--- 212 unchanged lines hidden ---