macromem.cc (10199:6cf40d777682) macromem.cc (10339:53278be85b40)
1/*
1/*
2 * Copyright (c) 2010-2013 ARM Limited
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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1102 UXTX, 0);
1103 } else {
1104 microOps[uopIdx++] = new MicroAddXiUop(machInst, rnsp, rnsp,
1105 totNumBytes);
1106 }
1107 }
1108
1109 for (int i = 0; i < numMarshalMicroops; ++i) {
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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1102 UXTX, 0);
1103 } else {
1104 microOps[uopIdx++] = new MicroAddXiUop(machInst, rnsp, rnsp,
1105 totNumBytes);
1106 }
1107 }
1108
1109 for (int i = 0; i < numMarshalMicroops; ++i) {
1110 microOps[uopIdx++] = new MicroDeintNeon64(
1111 machInst, vd + (RegIndex) (2 * i), vx, eSize, dataSize,
1112 numStructElems, numRegs, i /* step */);
1110 switch(numRegs) {
1111 case 1: microOps[uopIdx++] = new MicroDeintNeon64_1Reg(
1112 machInst, vd + (RegIndex) (2 * i), vx, eSize, dataSize,
1113 numStructElems, 1, i /* step */);
1114 break;
1115 case 2: microOps[uopIdx++] = new MicroDeintNeon64_2Reg(
1116 machInst, vd + (RegIndex) (2 * i), vx, eSize, dataSize,
1117 numStructElems, 2, i /* step */);
1118 break;
1119 case 3: microOps[uopIdx++] = new MicroDeintNeon64_3Reg(
1120 machInst, vd + (RegIndex) (2 * i), vx, eSize, dataSize,
1121 numStructElems, 3, i /* step */);
1122 break;
1123 case 4: microOps[uopIdx++] = new MicroDeintNeon64_4Reg(
1124 machInst, vd + (RegIndex) (2 * i), vx, eSize, dataSize,
1125 numStructElems, 4, i /* step */);
1126 break;
1127 default: panic("Invalid number of registers");
1128 }
1129
1113 }
1114
1115 assert(uopIdx == numMicroops);
1116
1117 for (int i = 0; i < numMicroops - 1; ++i) {
1118 microOps[i]->setDelayedCommit();
1119 }
1120 microOps[numMicroops - 1]->setLastMicroop();

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1145
1146 int numMarshalMicroops = totNumBytes > 32 ? 2 : 1;
1147 numMicroops += numMarshalMicroops;
1148
1149 microOps = new StaticInstPtr[numMicroops];
1150 unsigned uopIdx = 0;
1151
1152 for(int i = 0; i < numMarshalMicroops; ++i) {
1130 }
1131
1132 assert(uopIdx == numMicroops);
1133
1134 for (int i = 0; i < numMicroops - 1; ++i) {
1135 microOps[i]->setDelayedCommit();
1136 }
1137 microOps[numMicroops - 1]->setLastMicroop();

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1162
1163 int numMarshalMicroops = totNumBytes > 32 ? 2 : 1;
1164 numMicroops += numMarshalMicroops;
1165
1166 microOps = new StaticInstPtr[numMicroops];
1167 unsigned uopIdx = 0;
1168
1169 for(int i = 0; i < numMarshalMicroops; ++i) {
1153 microOps[uopIdx++] = new MicroIntNeon64(
1154 machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
1155 numStructElems, numRegs, i /* step */);
1170 switch (numRegs) {
1171 case 1: microOps[uopIdx++] = new MicroIntNeon64_1Reg(
1172 machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
1173 numStructElems, 1, i /* step */);
1174 break;
1175 case 2: microOps[uopIdx++] = new MicroIntNeon64_2Reg(
1176 machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
1177 numStructElems, 2, i /* step */);
1178 break;
1179 case 3: microOps[uopIdx++] = new MicroIntNeon64_3Reg(
1180 machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
1181 numStructElems, 3, i /* step */);
1182 break;
1183 case 4: microOps[uopIdx++] = new MicroIntNeon64_4Reg(
1184 machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
1185 numStructElems, 4, i /* step */);
1186 break;
1187 default: panic("Invalid number of registers");
1188 }
1156 }
1157
1158 uint32_t memaccessFlags = TLB::MustBeOne | (TLB::ArmFlags) eSize |
1159 TLB::AllowUnaligned;
1160
1161 int i = 0;
1162 for(; i < numMemMicroops - 1; ++i) {
1163 microOps[uopIdx++] = new MicroNeonStore64(

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1190
1191 uint32_t memaccessFlags = TLB::MustBeOne | (TLB::ArmFlags) eSize |
1192 TLB::AllowUnaligned;
1193
1194 int i = 0;
1195 for(; i < numMemMicroops - 1; ++i) {
1196 microOps[uopIdx++] = new MicroNeonStore64(

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