2c2
< * Copyright (c) 2010-2013 ARM Limited
---
> * Copyright (c) 2010-2014 ARM Limited
1110,1112c1110,1129
< microOps[uopIdx++] = new MicroDeintNeon64(
< machInst, vd + (RegIndex) (2 * i), vx, eSize, dataSize,
< numStructElems, numRegs, i /* step */);
---
> switch(numRegs) {
> case 1: microOps[uopIdx++] = new MicroDeintNeon64_1Reg(
> machInst, vd + (RegIndex) (2 * i), vx, eSize, dataSize,
> numStructElems, 1, i /* step */);
> break;
> case 2: microOps[uopIdx++] = new MicroDeintNeon64_2Reg(
> machInst, vd + (RegIndex) (2 * i), vx, eSize, dataSize,
> numStructElems, 2, i /* step */);
> break;
> case 3: microOps[uopIdx++] = new MicroDeintNeon64_3Reg(
> machInst, vd + (RegIndex) (2 * i), vx, eSize, dataSize,
> numStructElems, 3, i /* step */);
> break;
> case 4: microOps[uopIdx++] = new MicroDeintNeon64_4Reg(
> machInst, vd + (RegIndex) (2 * i), vx, eSize, dataSize,
> numStructElems, 4, i /* step */);
> break;
> default: panic("Invalid number of registers");
> }
>
1153,1155c1170,1188
< microOps[uopIdx++] = new MicroIntNeon64(
< machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
< numStructElems, numRegs, i /* step */);
---
> switch (numRegs) {
> case 1: microOps[uopIdx++] = new MicroIntNeon64_1Reg(
> machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
> numStructElems, 1, i /* step */);
> break;
> case 2: microOps[uopIdx++] = new MicroIntNeon64_2Reg(
> machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
> numStructElems, 2, i /* step */);
> break;
> case 3: microOps[uopIdx++] = new MicroIntNeon64_3Reg(
> machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
> numStructElems, 3, i /* step */);
> break;
> case 4: microOps[uopIdx++] = new MicroIntNeon64_4Reg(
> machInst, vx + (RegIndex) (2 * i), vd, eSize, dataSize,
> numStructElems, 4, i /* step */);
> break;
> default: panic("Invalid number of registers");
> }