1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#include "arch/arm/insts/macromem.hh"
44#include "arch/arm/decoder.hh"
45
46using namespace ArmISAInst;
47
48namespace ArmISA
49{
50
51MacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst,
52 OpClass __opClass, IntRegIndex rn,
53 bool index, bool up, bool user, bool writeback,
54 bool load, uint32_t reglist) :
55 PredMacroOp(mnem, machInst, __opClass)
56{
57 uint32_t regs = reglist;
58 uint32_t ones = number_of_ones(reglist);
59 // Remember that writeback adds a uop
60 numMicroops = ones + (writeback ? 1 : 0) + 1;
61 microOps = new StaticInstPtr[numMicroops];
62 uint32_t addr = 0;
63
64 if (!up)
65 addr = (ones << 2) - 4;
66
67 if (!index)
68 addr += 4;
69
70 // Add 0 to Rn and stick it in ureg0.
71 // This is equivalent to a move.
72 microOps[0] = new MicroAddiUop(machInst, INTREG_UREG0, rn, 0);
73
74 unsigned reg = 0;
75 bool force_user = user & !bits(reglist, 15);
76 bool exception_ret = user & bits(reglist, 15);
77
78 for (int i = 1; i < ones + 1; i++) {
79 // Find the next register.
80 while (!bits(regs, reg))
81 reg++;
82 replaceBits(regs, reg, 0);
83
84 unsigned regIdx = reg;
85 if (force_user) {
86 regIdx = intRegForceUser(regIdx);
87 }
88
89 if (load) {
90 if (reg == INTREG_PC && exception_ret) {
91 // This must be the exception return form of ldm.
92 microOps[i] =
93 new MicroLdrRetUop(machInst, regIdx,
94 INTREG_UREG0, up, addr);
95 } else {
96 microOps[i] =
97 new MicroLdrUop(machInst, regIdx, INTREG_UREG0, up, addr);
98 }
99 } else {
100 microOps[i] =
101 new MicroStrUop(machInst, regIdx, INTREG_UREG0, up, addr);
102 }
103
104 if (up)
105 addr += 4;
106 else
107 addr -= 4;
108 }
109
110 StaticInstPtr &lastUop = microOps[numMicroops - 1];
111 if (writeback) {
112 if (up) {
113 lastUop = new MicroAddiUop(machInst, rn, rn, ones * 4);
114 } else {
115 lastUop = new MicroSubiUop(machInst, rn, rn, ones * 4);
116 }
117 }
118 lastUop->setLastMicroop();
119}
120
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#include "arch/arm/insts/macromem.hh"
44#include "arch/arm/decoder.hh"
45
46using namespace ArmISAInst;
47
48namespace ArmISA
49{
50
51MacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst,
52 OpClass __opClass, IntRegIndex rn,
53 bool index, bool up, bool user, bool writeback,
54 bool load, uint32_t reglist) :
55 PredMacroOp(mnem, machInst, __opClass)
56{
57 uint32_t regs = reglist;
58 uint32_t ones = number_of_ones(reglist);
59 // Remember that writeback adds a uop
60 numMicroops = ones + (writeback ? 1 : 0) + 1;
61 microOps = new StaticInstPtr[numMicroops];
62 uint32_t addr = 0;
63
64 if (!up)
65 addr = (ones << 2) - 4;
66
67 if (!index)
68 addr += 4;
69
70 // Add 0 to Rn and stick it in ureg0.
71 // This is equivalent to a move.
72 microOps[0] = new MicroAddiUop(machInst, INTREG_UREG0, rn, 0);
73
74 unsigned reg = 0;
75 bool force_user = user & !bits(reglist, 15);
76 bool exception_ret = user & bits(reglist, 15);
77
78 for (int i = 1; i < ones + 1; i++) {
79 // Find the next register.
80 while (!bits(regs, reg))
81 reg++;
82 replaceBits(regs, reg, 0);
83
84 unsigned regIdx = reg;
85 if (force_user) {
86 regIdx = intRegForceUser(regIdx);
87 }
88
89 if (load) {
90 if (reg == INTREG_PC && exception_ret) {
91 // This must be the exception return form of ldm.
92 microOps[i] =
93 new MicroLdrRetUop(machInst, regIdx,
94 INTREG_UREG0, up, addr);
95 } else {
96 microOps[i] =
97 new MicroLdrUop(machInst, regIdx, INTREG_UREG0, up, addr);
98 }
99 } else {
100 microOps[i] =
101 new MicroStrUop(machInst, regIdx, INTREG_UREG0, up, addr);
102 }
103
104 if (up)
105 addr += 4;
106 else
107 addr -= 4;
108 }
109
110 StaticInstPtr &lastUop = microOps[numMicroops - 1];
111 if (writeback) {
112 if (up) {
113 lastUop = new MicroAddiUop(machInst, rn, rn, ones * 4);
114 } else {
115 lastUop = new MicroSubiUop(machInst, rn, rn, ones * 4);
116 }
117 }
118 lastUop->setLastMicroop();
119}
120
|
| 121MacroVFPMemOp::MacroVFPMemOp(const char *mnem, ExtMachInst machInst,
122 OpClass __opClass, IntRegIndex rn,
123 RegIndex vd, bool single, bool up,
124 bool writeback, bool load, uint32_t offset) :
125 PredMacroOp(mnem, machInst, __opClass)
126{
127 const int maxMicroops = 17;
128 microOps = new StaticInstPtr[maxMicroops];
129 int i = 0;
130
131 // The lowest order bit selects fldmx (set) or fldmd (clear). These seem
132 // to be functionally identical except that fldmx is deprecated. For now
133 // we'll assume they're otherwise interchangable.
134 int count = (single ? offset : (offset / 2));
135 if (count == 0 || count > NumFloatArchRegs)
136 warn_once("Bad offset field for VFP load/store multiple.\n");
137 if (count == 0) {
138 // Force there to be at least one microop so the macroop makes sense.
139 writeback = true;
140 }
141 if (count > NumFloatArchRegs)
142 count = NumFloatArchRegs;
143
144 uint32_t addr = 0;
145
146 if (up)
147 addr = -4 * offset;
148
149 for (int j = 0; j < count; j++) {
150 if (load) {
151 microOps[i++] = new MicroLdrFpUop(machInst, vd++, rn,
152 true, addr);
153 if (!single)
154 microOps[i++] = new MicroLdrFpUop(machInst, vd++, rn,
155 true, addr + 4);
156 } else {
157 microOps[i++] = new MicroStrFpUop(machInst, vd++, rn,
158 true, addr);
159 if (!single)
160 microOps[i++] = new MicroStrFpUop(machInst, vd++, rn,
161 true, addr + 4);
162 }
163 addr += (single ? 4 : 8);
164 }
165
166 if (writeback) {
167 if (up) {
168 microOps[i++] =
169 new MicroAddiUop(machInst, rn, rn, 4 * offset);
170 } else {
171 microOps[i++] =
172 new MicroSubiUop(machInst, rn, rn, 4 * offset);
173 }
174 }
175
176 numMicroops = i;
177 assert(numMicroops <= maxMicroops);
178 microOps[numMicroops - 1]->setLastMicroop();
|