1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#include "arch/arm/insts/macromem.hh"
44#include "arch/arm/decoder.hh"
45
46using namespace ArmISAInst;
47
48namespace ArmISA
49{
50
51MacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst,
52 OpClass __opClass, IntRegIndex rn,
53 bool index, bool up, bool user, bool writeback,
54 bool load, uint32_t reglist) :
55 PredMacroOp(mnem, machInst, __opClass)
56{
57 uint32_t regs = reglist;
58 uint32_t ones = number_of_ones(reglist);
59 // Remember that writeback adds a uop
60 numMicroops = ones + (writeback ? 1 : 0) + 1;
61 microOps = new StaticInstPtr[numMicroops];
62 uint32_t addr = 0;
63
64 if (!up)
65 addr = (ones << 2) - 4;
66
67 if (!index)
68 addr += 4;
69
70 StaticInstPtr *uop = microOps;
71 StaticInstPtr wbUop;
72 if (writeback) {
73 if (up) {
74 wbUop = new MicroAddiUop(machInst, rn, rn, ones * 4);
75 } else {
76 wbUop = new MicroSubiUop(machInst, rn, rn, ones * 4);
77 }
78 }
79
80 // Add 0 to Rn and stick it in ureg0.
81 // This is equivalent to a move.
82 *uop = new MicroAddiUop(machInst, INTREG_UREG0, rn, 0);
83
84 // Write back at the start for loads. This covers the ldm exception return
85 // case where the base needs to be written in the old mode. Stores may need
86 // the original value of the base, but they don't change mode and can
87 // write back at the end like before.
88 if (load && writeback) {
89 *++uop = wbUop;
90 }
91
92 unsigned reg = 0;
93 bool force_user = user & !bits(reglist, 15);
94 bool exception_ret = user & bits(reglist, 15);
95
96 for (int i = 0; i < ones; i++) {
97 // Find the next register.
98 while (!bits(regs, reg))
99 reg++;
100 replaceBits(regs, reg, 0);
101
102 unsigned regIdx = reg;
103 if (force_user) {
104 regIdx = intRegInMode(MODE_USER, regIdx);
105 }
106
107 if (load) {
108 if (reg == INTREG_PC && exception_ret) {
109 // This must be the exception return form of ldm.
110 *++uop = new MicroLdrRetUop(machInst, regIdx,
111 INTREG_UREG0, up, addr);
112 } else {
113 *++uop = new MicroLdrUop(machInst, regIdx,
114 INTREG_UREG0, up, addr);
115 }
116 } else {
117 *++uop = new MicroStrUop(machInst, regIdx, INTREG_UREG0, up, addr);
118 }
119
120 if (up)
121 addr += 4;
122 else
123 addr -= 4;
124 }
125
126 if (!load && writeback) {
127 *++uop = wbUop;
128 }
129
130 (*uop)->setLastMicroop();
131
132 for (StaticInstPtr *curUop = microOps;
133 !(*curUop)->isLastMicroop(); curUop++) {
134 MicroOp * uopPtr = dynamic_cast<MicroOp *>(curUop->get());
135 assert(uopPtr);
136 uopPtr->setDelayedCommit();
137 }
138}
139
140MacroVFPMemOp::MacroVFPMemOp(const char *mnem, ExtMachInst machInst,
141 OpClass __opClass, IntRegIndex rn,
142 RegIndex vd, bool single, bool up,
143 bool writeback, bool load, uint32_t offset) :
144 PredMacroOp(mnem, machInst, __opClass)
145{
146 int i = 0;
147
148 // The lowest order bit selects fldmx (set) or fldmd (clear). These seem
149 // to be functionally identical except that fldmx is deprecated. For now
150 // we'll assume they're otherwise interchangable.
151 int count = (single ? offset : (offset / 2));
152 if (count == 0 || count > NumFloatArchRegs)
153 warn_once("Bad offset field for VFP load/store multiple.\n");
154 if (count == 0) {
155 // Force there to be at least one microop so the macroop makes sense.
156 writeback = true;
157 }
158 if (count > NumFloatArchRegs)
159 count = NumFloatArchRegs;
160
161 numMicroops = count * (single ? 1 : 2) + (writeback ? 1 : 0);
162 microOps = new StaticInstPtr[numMicroops];
163
164 int64_t addr = 0;
165
166 if (!up)
167 addr = 4 * offset;
168
169 bool tempUp = up;
170 for (int j = 0; j < count; j++) {
171 if (load) {
172 microOps[i++] = new MicroLdrFpUop(machInst, vd++, rn,
173 tempUp, addr);
174 if (!single)
175 microOps[i++] = new MicroLdrFpUop(machInst, vd++, rn, tempUp,
176 addr + (up ? 4 : -4));
177 } else {
178 microOps[i++] = new MicroStrFpUop(machInst, vd++, rn,
179 tempUp, addr);
180 if (!single)
181 microOps[i++] = new MicroStrFpUop(machInst, vd++, rn, tempUp,
182 addr + (up ? 4 : -4));
183 }
184 if (!tempUp) {
185 addr -= (single ? 4 : 8);
186 // The microops don't handle negative displacement, so turn if we
187 // hit zero, flip polarity and start adding.
188 if (addr <= 0) {
189 tempUp = true;
190 addr = -addr;
191 }
192 } else {
193 addr += (single ? 4 : 8);
194 }
195 }
196
197 if (writeback) {
198 if (up) {
199 microOps[i++] =
200 new MicroAddiUop(machInst, rn, rn, 4 * offset);
201 } else {
202 microOps[i++] =
203 new MicroSubiUop(machInst, rn, rn, 4 * offset);
204 }
205 }
206
207 assert(numMicroops == i);
208 microOps[numMicroops - 1]->setLastMicroop();
209
210 for (StaticInstPtr *curUop = microOps;
211 !(*curUop)->isLastMicroop(); curUop++) {
212 MicroOp * uopPtr = dynamic_cast<MicroOp *>(curUop->get());
213 assert(uopPtr);
214 uopPtr->setDelayedCommit();
215 }
216}
217
218std::string
219MicroIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
220{
221 std::stringstream ss;
222 printMnemonic(ss);
223 printReg(ss, ura);
224 ss << ", ";
225 printReg(ss, urb);
226 ss << ", ";
227 ccprintf(ss, "#%d", imm);
228 return ss.str();
229}
230
231std::string
232MicroMemOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
233{
234 std::stringstream ss;
235 printMnemonic(ss);
236 printReg(ss, ura);
237 ss << ", [";
238 printReg(ss, urb);
239 ss << ", ";
240 ccprintf(ss, "#%d", imm);
241 ss << "]";
242 return ss.str();
243}
244
245}