1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#include <sstream>
44
45#include "arch/arm/insts/macromem.hh"
46#include "arch/arm/generated/decoder.hh"
47
48using namespace std;
49using namespace ArmISAInst;
50
51namespace ArmISA
52{
53
54MacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst,

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172 for (StaticInstPtr *curUop = microOps;
173 !(*curUop)->isLastMicroop(); curUop++) {
174 MicroOp * uopPtr = dynamic_cast<MicroOp *>(curUop->get());
175 assert(uopPtr);
176 uopPtr->setDelayedCommit();
177 }
178}
179
180VldMultOp::VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
181 unsigned elems, RegIndex rn, RegIndex vd, unsigned regs,
182 unsigned inc, uint32_t size, uint32_t align, RegIndex rm) :
183 PredMacroOp(mnem, machInst, __opClass)
184{
185 assert(regs > 0 && regs <= 4);
186 assert(regs % elems == 0);
187
188 numMicroops = (regs > 2) ? 2 : 1;
189 bool wb = (rm != 15);
190 bool deinterleave = (elems > 1);
191
192 if (wb) numMicroops++;
193 if (deinterleave) numMicroops += (regs / elems);
194 microOps = new StaticInstPtr[numMicroops];
195
196 RegIndex rMid = deinterleave ? NumFloatArchRegs : vd * 2;
197
198 uint32_t noAlign = TLB::MustBeOne;
199
200 unsigned uopIdx = 0;
201 switch (regs) {
202 case 4:
203 microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon16Uop>(
204 size, machInst, rMid, rn, 0, align);

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290
291 numMicroops = 1;
292 bool wb = (rm != 15);
293
294 if (wb) numMicroops++;
295 numMicroops += (regs / elems);
296 microOps = new StaticInstPtr[numMicroops];
297
298 RegIndex ufp0 = NumFloatArchRegs;
299
300 unsigned uopIdx = 0;
301 switch (loadSize) {
302 case 1:
303 microOps[uopIdx++] = new MicroLdrNeon1Uop<uint8_t>(
304 machInst, ufp0, rn, 0, align);
305 break;
306 case 2:

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551 bool interleave = (elems > 1);
552
553 if (wb) numMicroops++;
554 if (interleave) numMicroops += (regs / elems);
555 microOps = new StaticInstPtr[numMicroops];
556
557 uint32_t noAlign = TLB::MustBeOne;
558
559 RegIndex rMid = interleave ? NumFloatArchRegs : vd * 2;
560
561 unsigned uopIdx = 0;
562 if (interleave) {
563 switch (elems) {
564 case 4:
565 assert(regs == 4);
566 microOps[uopIdx++] = newNeonMixInst<MicroInterNeon8Uop>(
567 size, machInst, rMid, vd * 2, inc * 2);

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652
653 numMicroops = 1;
654 bool wb = (rm != 15);
655
656 if (wb) numMicroops++;
657 numMicroops += (regs / elems);
658 microOps = new StaticInstPtr[numMicroops];
659
660 RegIndex ufp0 = NumFloatArchRegs;
661
662 unsigned uopIdx = 0;
663 switch (elems) {
664 case 4:
665 assert(regs == 4);
666 switch (size) {
667 case 0:
668 microOps[uopIdx++] = new MicroPackNeon8to2Uop<uint8_t>(

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829 for (unsigned i = 0; i < numMicroops - 1; i++) {
830 MicroOp * uopPtr = dynamic_cast<MicroOp *>(microOps[i].get());
831 assert(uopPtr);
832 uopPtr->setDelayedCommit();
833 }
834 microOps[numMicroops - 1]->setLastMicroop();
835}
836
837MacroVFPMemOp::MacroVFPMemOp(const char *mnem, ExtMachInst machInst,
838 OpClass __opClass, IntRegIndex rn,
839 RegIndex vd, bool single, bool up,
840 bool writeback, bool load, uint32_t offset) :
841 PredMacroOp(mnem, machInst, __opClass)
842{
843 int i = 0;
844
845 // The lowest order bit selects fldmx (set) or fldmd (clear). These seem
846 // to be functionally identical except that fldmx is deprecated. For now
847 // we'll assume they're otherwise interchangable.
848 int count = (single ? offset : (offset / 2));
849 if (count == 0 || count > NumFloatArchRegs)
850 warn_once("Bad offset field for VFP load/store multiple.\n");
851 if (count == 0) {
852 // Force there to be at least one microop so the macroop makes sense.
853 writeback = true;
854 }
855 if (count > NumFloatArchRegs)
856 count = NumFloatArchRegs;
857
858 numMicroops = count * (single ? 1 : 2) + (writeback ? 1 : 0);
859 microOps = new StaticInstPtr[numMicroops];
860
861 int64_t addr = 0;
862
863 if (!up)
864 addr = 4 * offset;

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929 ss << ", ";
930 printReg(ss, urb);
931 ss << ", ";
932 ccprintf(ss, "#%d", imm);
933 return ss.str();
934}
935
936std::string
937MicroSetPCCPSR::generateDisassembly(Addr pc, const SymbolTable *symtab) const
938{
939 std::stringstream ss;
940 printMnemonic(ss);
941 ss << "[PC,CPSR]";
942 return ss.str();
943}
944
945std::string
946MicroIntMov::generateDisassembly(Addr pc, const SymbolTable *symtab) const
947{
948 std::stringstream ss;
949 printMnemonic(ss);
950 printReg(ss, ura);
951 ss << ", ";
952 printReg(ss, urb);
953 return ss.str();

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