1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#include "arch/arm/insts/macromem.hh"
44#include "arch/arm/decoder.hh"
45
46using namespace ArmISAInst;
47
48namespace ArmISA
49{
50
51MacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst,
52 OpClass __opClass, IntRegIndex rn,
53 bool index, bool up, bool user, bool writeback,

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175 microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon16Uop>(
176 size, machInst, rMid, rn, 0, align);
177 break;
178 case 1:
179 microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon8Uop>(
180 size, machInst, rMid, rn, 0, align);
181 break;
182 default:
183 panic("Unrecognized number of registers %d.\n", regs);
184 }
185 if (wb) {
186 if (rm != 15 && rm != 13) {
187 microOps[uopIdx++] =
188 new MicroAddUop(machInst, rn, rn, rm, 0, ArmISA::LSL);
189 } else {
190 microOps[uopIdx++] =
191 new MicroAddiUop(machInst, rn, rn, regs * 8);

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211 microOps[uopIdx++] = newNeonMixInst<MicroDeintNeon4Uop>(
212 size, machInst, vd * 2 + 2, rMid + 4, inc * 2);
213 } else {
214 microOps[uopIdx++] = newNeonMixInst<MicroDeintNeon4Uop>(
215 size, machInst, vd * 2, rMid, inc * 2);
216 }
217 break;
218 default:
219 panic("Bad number of elements to deinterleave %d.\n", elems);
220 }
221 }
222 assert(uopIdx == numMicroops);
223
224 for (unsigned i = 0; i < numMicroops - 1; i++) {
225 MicroOp * uopPtr = dynamic_cast<MicroOp *>(microOps[i].get());
226 assert(uopPtr);
227 uopPtr->setDelayedCommit();

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310 microOps[uopIdx++] = new MicroLdrNeon12Uop<uint32_t>(
311 machInst, ufp0, rn, 0, align);
312 break;
313 case 16:
314 microOps[uopIdx++] = new MicroLdrNeon16Uop<uint32_t>(
315 machInst, ufp0, rn, 0, align);
316 break;
317 default:
318 panic("Unrecognized load size %d.\n", regs);
319 }
320 if (wb) {
321 if (rm != 15 && rm != 13) {
322 microOps[uopIdx++] =
323 new MicroAddUop(machInst, rn, rn, rm, 0, ArmISA::LSL);
324 } else {
325 microOps[uopIdx++] =
326 new MicroAddiUop(machInst, rn, rn, loadSize);

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353 microOps[uopIdx++] = new MicroUnpackAllNeon4to8Uop<uint32_t>(
354 machInst, vd * 2, ufp0, inc * 2);
355 } else {
356 microOps[uopIdx++] = new MicroUnpackNeon4to8Uop<uint32_t>(
357 machInst, vd * 2, ufp0, inc * 2, lane);
358 }
359 break;
360 default:
361 panic("Bad size %d.\n", size);
362 break;
363 }
364 break;
365 case 3:
366 assert(regs == 3);
367 switch (size) {
368 case 0:
369 if (all) {

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388 microOps[uopIdx++] = new MicroUnpackAllNeon4to6Uop<uint32_t>(
389 machInst, vd * 2, ufp0, inc * 2);
390 } else {
391 microOps[uopIdx++] = new MicroUnpackNeon4to6Uop<uint32_t>(
392 machInst, vd * 2, ufp0, inc * 2, lane);
393 }
394 break;
395 default:
396 panic("Bad size %d.\n", size);
397 break;
398 }
399 break;
400 case 2:
401 assert(regs == 2);
402 assert(loadRegs <= 2);
403 switch (size) {
404 case 0:

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424 microOps[uopIdx++] = new MicroUnpackAllNeon2to4Uop<uint32_t>(
425 machInst, vd * 2, ufp0, inc * 2);
426 } else {
427 microOps[uopIdx++] = new MicroUnpackNeon2to4Uop<uint32_t>(
428 machInst, vd * 2, ufp0, inc * 2, lane);
429 }
430 break;
431 default:
432 panic("Bad size %d.\n", size);
433 break;
434 }
435 break;
436 case 1:
437 assert(regs == 1 || (all && regs == 2));
438 assert(loadRegs <= 2);
439 for (unsigned offset = 0; offset < regs; offset++) {
440 switch (size) {

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467 machInst, (vd + offset) * 2, ufp0, inc * 2);
468 } else {
469 microOps[uopIdx++] =
470 new MicroUnpackNeon2to2Uop<uint32_t>(
471 machInst, (vd + offset) * 2, ufp0, inc * 2, lane);
472 }
473 break;
474 default:
475 panic("Bad size %d.\n", size);
476 break;
477 }
478 }
479 break;
480 default:
481 panic("Bad number of elements to unpack %d.\n", elems);
482 }
483 assert(uopIdx == numMicroops);
484
485 for (unsigned i = 0; i < numMicroops - 1; i++) {
486 MicroOp * uopPtr = dynamic_cast<MicroOp *>(microOps[i].get());
487 assert(uopPtr);
488 uopPtr->setDelayedCommit();
489 }

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531 microOps[uopIdx++] = newNeonMixInst<MicroInterNeon4Uop>(
532 size, machInst, rMid + 4, vd * 2 + 2, inc * 2);
533 } else {
534 microOps[uopIdx++] = newNeonMixInst<MicroInterNeon4Uop>(
535 size, machInst, rMid, vd * 2, inc * 2);
536 }
537 break;
538 default:
539 panic("Bad number of elements to interleave %d.\n", elems);
540 }
541 }
542 switch (regs) {
543 case 4:
544 microOps[uopIdx++] = newNeonMemInst<MicroStrNeon16Uop>(
545 size, machInst, rMid, rn, 0, align);
546 microOps[uopIdx++] = newNeonMemInst<MicroStrNeon16Uop>(
547 size, machInst, rMid + 4, rn, 16, noAlign);

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556 microOps[uopIdx++] = newNeonMemInst<MicroStrNeon16Uop>(
557 size, machInst, rMid, rn, 0, align);
558 break;
559 case 1:
560 microOps[uopIdx++] = newNeonMemInst<MicroStrNeon8Uop>(
561 size, machInst, rMid, rn, 0, align);
562 break;
563 default:
564 panic("Unrecognized number of registers %d.\n", regs);
565 }
566 if (wb) {
567 if (rm != 15 && rm != 13) {
568 microOps[uopIdx++] =
569 new MicroAddUop(machInst, rn, rn, rm, 0, ArmISA::LSL);
570 } else {
571 microOps[uopIdx++] =
572 new MicroAddiUop(machInst, rn, rn, regs * 8);

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622 microOps[uopIdx++] = new MicroPackNeon8to2Uop<uint16_t>(
623 machInst, ufp0, vd * 2, inc * 2, lane);
624 break;
625 case 2:
626 microOps[uopIdx++] = new MicroPackNeon8to4Uop<uint32_t>(
627 machInst, ufp0, vd * 2, inc * 2, lane);
628 break;
629 default:
630 panic("Bad size %d.\n", size);
631 break;
632 }
633 break;
634 case 3:
635 assert(regs == 3);
636 switch (size) {
637 case 0:
638 microOps[uopIdx++] = new MicroPackNeon6to2Uop<uint8_t>(
639 machInst, ufp0, vd * 2, inc * 2, lane);
640 break;
641 case 1:
642 microOps[uopIdx++] = new MicroPackNeon6to2Uop<uint16_t>(
643 machInst, ufp0, vd * 2, inc * 2, lane);
644 break;
645 case 2:
646 microOps[uopIdx++] = new MicroPackNeon6to4Uop<uint32_t>(
647 machInst, ufp0, vd * 2, inc * 2, lane);
648 break;
649 default:
650 panic("Bad size %d.\n", size);
651 break;
652 }
653 break;
654 case 2:
655 assert(regs == 2);
656 assert(storeRegs <= 2);
657 switch (size) {
658 case 0:

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663 microOps[uopIdx++] = new MicroPackNeon4to2Uop<uint16_t>(
664 machInst, ufp0, vd * 2, inc * 2, lane);
665 break;
666 case 2:
667 microOps[uopIdx++] = new MicroPackNeon4to2Uop<uint32_t>(
668 machInst, ufp0, vd * 2, inc * 2, lane);
669 break;
670 default:
671 panic("Bad size %d.\n", size);
672 break;
673 }
674 break;
675 case 1:
676 assert(regs == 1 || (all && regs == 2));
677 assert(storeRegs <= 2);
678 for (unsigned offset = 0; offset < regs; offset++) {
679 switch (size) {

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685 microOps[uopIdx++] = new MicroPackNeon2to2Uop<uint16_t>(
686 machInst, ufp0, (vd + offset) * 2, inc * 2, lane);
687 break;
688 case 2:
689 microOps[uopIdx++] = new MicroPackNeon2to2Uop<uint32_t>(
690 machInst, ufp0, (vd + offset) * 2, inc * 2, lane);
691 break;
692 default:
693 panic("Bad size %d.\n", size);
694 break;
695 }
696 }
697 break;
698 default:
699 panic("Bad number of elements to pack %d.\n", elems);
700 }
701 switch (storeSize) {
702 case 1:
703 microOps[uopIdx++] = new MicroStrNeon1Uop<uint8_t>(
704 machInst, ufp0, rn, 0, align);
705 break;
706 case 2:
707 if (eBytes == 2) {

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752 microOps[uopIdx++] = new MicroStrNeon12Uop<uint32_t>(
753 machInst, ufp0, rn, 0, align);
754 break;
755 case 16:
756 microOps[uopIdx++] = new MicroStrNeon16Uop<uint32_t>(
757 machInst, ufp0, rn, 0, align);
758 break;
759 default:
760 panic("Unrecognized store size %d.\n", regs);
761 }
762 if (wb) {
763 if (rm != 15 && rm != 13) {
764 microOps[uopIdx++] =
765 new MicroAddUop(machInst, rn, rn, rm, 0, ArmISA::LSL);
766 } else {
767 microOps[uopIdx++] =
768 new MicroAddiUop(machInst, rn, rn, storeSize);

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