1/*
2* Copyright (c) 2012-2013, 2017-2018 ARM Limited
3* All rights reserved
4*
5* The license below extends only to copyright in the software and shall
6* not be construed as granting a license to any other intellectual
7* property including but not limited to intellectual property relating
8* to a hardware implementation of the functionality of the software

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37* Authors: Edmund Grimley Evans
38* Thomas Grocutt
39*/
40
41#include <stdint.h>
42
43#include <cassert>
44
45#include "fplib.hh"
46
47namespace ArmISA
48{
49
50#define FPLIB_RN 0
51#define FPLIB_RP 1
52#define FPLIB_RM 2

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3735 break;
3736 case FPRounding_NEGINF:
3737 overflow_to_inf = sgn;
3738 break;
3739 case FPRounding_ZERO:
3740 overflow_to_inf = false;
3741 break;
3742 default:
3743 assert(0);
3744 }
3745 result = overflow_to_inf ? fp16_infinity(sgn) : fp16_max_normal(sgn);
3746 flags |= FPLIB_OFC | FPLIB_IXC;
3747 } else if (fpscr.fz16 && exp >= 2 * FP16_EXP_BIAS - 1) {
3748 result = fp16_zero(sgn);
3749 flags |= FPLIB_UFC;
3750 } else {
3751 exp += FP16_EXP_BITS;

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3797 break;
3798 case FPRounding_NEGINF:
3799 overflow_to_inf = sgn;
3800 break;
3801 case FPRounding_ZERO:
3802 overflow_to_inf = false;
3803 break;
3804 default:
3805 assert(0);
3806 }
3807 result = overflow_to_inf ? fp32_infinity(sgn) : fp32_max_normal(sgn);
3808 flags |= FPLIB_OFC | FPLIB_IXC;
3809 } else if (fpscr.fz && exp >= 2 * FP32_EXP_BIAS - 1) {
3810 result = fp32_zero(sgn);
3811 flags |= FPLIB_UFC;
3812 } else {
3813 exp += FP32_EXP_BITS;

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3859 break;
3860 case FPRounding_NEGINF:
3861 overflow_to_inf = sgn;
3862 break;
3863 case FPRounding_ZERO:
3864 overflow_to_inf = false;
3865 break;
3866 default:
3867 assert(0);
3868 }
3869 result = overflow_to_inf ? fp64_infinity(sgn) : fp64_max_normal(sgn);
3870 flags |= FPLIB_OFC | FPLIB_IXC;
3871 } else if (fpscr.fz && exp >= 2 * FP64_EXP_BIAS - 1) {
3872 result = fp64_zero(sgn);
3873 flags |= FPLIB_UFC;
3874 } else {
3875 exp += FP64_EXP_BITS;

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4103 x += err && sgn;
4104 break;
4105 case FPRounding_ZERO:
4106 break;
4107 case FPRounding_TIEAWAY:
4108 x += err >> 1;
4109 break;
4110 default:
4111 assert(0);
4112 }
4113
4114 if (x == 0) {
4115 result = fp16_zero(sgn);
4116 } else {
4117 exp = expint;
4118 mnt = fp16_normalise(x, &exp);
4119 result = fp16_pack(sgn, exp + FP16_EXP_BITS, mnt >> FP16_EXP_BITS);

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4168 x += err && sgn;
4169 break;
4170 case FPRounding_ZERO:
4171 break;
4172 case FPRounding_TIEAWAY:
4173 x += err >> 1;
4174 break;
4175 default:
4176 assert(0);
4177 }
4178
4179 if (x == 0) {
4180 result = fp32_zero(sgn);
4181 } else {
4182 exp = expint;
4183 mnt = fp32_normalise(x, &exp);
4184 result = fp32_pack(sgn, exp + FP32_EXP_BITS, mnt >> FP32_EXP_BITS);

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4233 x += err && sgn;
4234 break;
4235 case FPRounding_ZERO:
4236 break;
4237 case FPRounding_TIEAWAY:
4238 x += err >> 1;
4239 break;
4240 default:
4241 assert(0);
4242 }
4243
4244 if (x == 0) {
4245 result = fp64_zero(sgn);
4246 } else {
4247 exp = expint;
4248 mnt = fp64_normalise(x, &exp);
4249 result = fp64_pack(sgn, exp + FP64_EXP_BITS, mnt >> FP64_EXP_BITS);

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4570 x += err && sgn;
4571 break;
4572 case FPRounding_ZERO:
4573 break;
4574 case FPRounding_TIEAWAY:
4575 x += err >> 1;
4576 break;
4577 default:
4578 assert(0);
4579 }
4580
4581 if (u ? sgn && x : x > (1ULL << (FP64_BITS - 1)) - !sgn) {
4582 *flags = FPLIB_IOC;
4583 return ((uint64_t)!u << (FP64_BITS - 1)) - !sgn;
4584 }
4585
4586 if (err) {

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