1/* 2 * Copyright (c) 2011-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39#ifndef __ARCH_ARM_INSTS_DATA64_HH__ 40#define __ARCH_ARM_INSTS_DATA64_HH__ 41 42#include "arch/arm/insts/static_inst.hh" 43#include "base/trace.hh" 44 45namespace ArmISA 46{ 47 48class DataXImmOp : public ArmStaticInst 49{ 50 protected: 51 IntRegIndex dest, op1; 52 uint64_t imm; 53 54 DataXImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 55 IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm) : 56 ArmStaticInst(mnem, _machInst, __opClass), 57 dest(_dest), op1(_op1), imm(_imm) 58 {} 59
| 1/* 2 * Copyright (c) 2011-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39#ifndef __ARCH_ARM_INSTS_DATA64_HH__ 40#define __ARCH_ARM_INSTS_DATA64_HH__ 41 42#include "arch/arm/insts/static_inst.hh" 43#include "base/trace.hh" 44 45namespace ArmISA 46{ 47 48class DataXImmOp : public ArmStaticInst 49{ 50 protected: 51 IntRegIndex dest, op1; 52 uint64_t imm; 53 54 DataXImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 55 IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm) : 56 ArmStaticInst(mnem, _machInst, __opClass), 57 dest(_dest), op1(_op1), imm(_imm) 58 {} 59
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60 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
| 60 std::string generateDisassembly( 61 Addr pc, const SymbolTable *symtab) const override;
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61}; 62 63class DataXImmOnlyOp : public ArmStaticInst 64{ 65 protected: 66 IntRegIndex dest; 67 uint64_t imm; 68 69 DataXImmOnlyOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 70 IntRegIndex _dest, uint64_t _imm) : 71 ArmStaticInst(mnem, _machInst, __opClass), 72 dest(_dest), imm(_imm) 73 {} 74
| 62}; 63 64class DataXImmOnlyOp : public ArmStaticInst 65{ 66 protected: 67 IntRegIndex dest; 68 uint64_t imm; 69 70 DataXImmOnlyOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 71 IntRegIndex _dest, uint64_t _imm) : 72 ArmStaticInst(mnem, _machInst, __opClass), 73 dest(_dest), imm(_imm) 74 {} 75
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75 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
| 76 std::string generateDisassembly( 77 Addr pc, const SymbolTable *symtab) const override;
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76}; 77 78class DataXSRegOp : public ArmStaticInst 79{ 80 protected: 81 IntRegIndex dest, op1, op2; 82 int32_t shiftAmt; 83 ArmShiftType shiftType; 84 85 DataXSRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 86 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 87 int32_t _shiftAmt, ArmShiftType _shiftType) : 88 ArmStaticInst(mnem, _machInst, __opClass), 89 dest(_dest), op1(_op1), op2(_op2), 90 shiftAmt(_shiftAmt), shiftType(_shiftType) 91 {} 92
| 78}; 79 80class DataXSRegOp : public ArmStaticInst 81{ 82 protected: 83 IntRegIndex dest, op1, op2; 84 int32_t shiftAmt; 85 ArmShiftType shiftType; 86 87 DataXSRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 88 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 89 int32_t _shiftAmt, ArmShiftType _shiftType) : 90 ArmStaticInst(mnem, _machInst, __opClass), 91 dest(_dest), op1(_op1), op2(_op2), 92 shiftAmt(_shiftAmt), shiftType(_shiftType) 93 {} 94
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93 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
| 95 std::string generateDisassembly( 96 Addr pc, const SymbolTable *symtab) const override;
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94}; 95 96class DataXERegOp : public ArmStaticInst 97{ 98 protected: 99 IntRegIndex dest, op1, op2; 100 ArmExtendType extendType; 101 int32_t shiftAmt; 102 103 DataXERegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 104 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 105 ArmExtendType _extendType, int32_t _shiftAmt) : 106 ArmStaticInst(mnem, _machInst, __opClass), 107 dest(_dest), op1(_op1), op2(_op2), 108 extendType(_extendType), shiftAmt(_shiftAmt) 109 {} 110
| 97}; 98 99class DataXERegOp : public ArmStaticInst 100{ 101 protected: 102 IntRegIndex dest, op1, op2; 103 ArmExtendType extendType; 104 int32_t shiftAmt; 105 106 DataXERegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 107 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 108 ArmExtendType _extendType, int32_t _shiftAmt) : 109 ArmStaticInst(mnem, _machInst, __opClass), 110 dest(_dest), op1(_op1), op2(_op2), 111 extendType(_extendType), shiftAmt(_shiftAmt) 112 {} 113
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111 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
| 114 std::string generateDisassembly( 115 Addr pc, const SymbolTable *symtab) const override;
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112}; 113 114class DataX1RegOp : public ArmStaticInst 115{ 116 protected: 117 IntRegIndex dest, op1; 118 119 DataX1RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 120 IntRegIndex _dest, IntRegIndex _op1) : 121 ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1) 122 {} 123
| 116}; 117 118class DataX1RegOp : public ArmStaticInst 119{ 120 protected: 121 IntRegIndex dest, op1; 122 123 DataX1RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 124 IntRegIndex _dest, IntRegIndex _op1) : 125 ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1) 126 {} 127
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124 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
| 128 std::string generateDisassembly( 129 Addr pc, const SymbolTable *symtab) const override;
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125}; 126 127class DataX1RegImmOp : public ArmStaticInst 128{ 129 protected: 130 IntRegIndex dest, op1; 131 uint64_t imm; 132 133 DataX1RegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 134 IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm) : 135 ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1), 136 imm(_imm) 137 {} 138
| 130}; 131 132class DataX1RegImmOp : public ArmStaticInst 133{ 134 protected: 135 IntRegIndex dest, op1; 136 uint64_t imm; 137 138 DataX1RegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 139 IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm) : 140 ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1), 141 imm(_imm) 142 {} 143
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139 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
| 144 std::string generateDisassembly( 145 Addr pc, const SymbolTable *symtab) const override;
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140}; 141 142class DataX1Reg2ImmOp : public ArmStaticInst 143{ 144 protected: 145 IntRegIndex dest, op1; 146 uint64_t imm1, imm2; 147 148 DataX1Reg2ImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 149 IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm1, 150 uint64_t _imm2) : 151 ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1), 152 imm1(_imm1), imm2(_imm2) 153 {} 154
| 146}; 147 148class DataX1Reg2ImmOp : public ArmStaticInst 149{ 150 protected: 151 IntRegIndex dest, op1; 152 uint64_t imm1, imm2; 153 154 DataX1Reg2ImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 155 IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm1, 156 uint64_t _imm2) : 157 ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1), 158 imm1(_imm1), imm2(_imm2) 159 {} 160
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155 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
| 161 std::string generateDisassembly( 162 Addr pc, const SymbolTable *symtab) const override;
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156}; 157 158class DataX2RegOp : public ArmStaticInst 159{ 160 protected: 161 IntRegIndex dest, op1, op2; 162 163 DataX2RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 164 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) : 165 ArmStaticInst(mnem, _machInst, __opClass), 166 dest(_dest), op1(_op1), op2(_op2) 167 {} 168
| 163}; 164 165class DataX2RegOp : public ArmStaticInst 166{ 167 protected: 168 IntRegIndex dest, op1, op2; 169 170 DataX2RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 171 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) : 172 ArmStaticInst(mnem, _machInst, __opClass), 173 dest(_dest), op1(_op1), op2(_op2) 174 {} 175
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169 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
| 176 std::string generateDisassembly( 177 Addr pc, const SymbolTable *symtab) const override;
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170}; 171 172class DataX2RegImmOp : public ArmStaticInst 173{ 174 protected: 175 IntRegIndex dest, op1, op2; 176 uint64_t imm; 177 178 DataX2RegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 179 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 180 uint64_t _imm) : 181 ArmStaticInst(mnem, _machInst, __opClass), 182 dest(_dest), op1(_op1), op2(_op2), imm(_imm) 183 {} 184
| 178}; 179 180class DataX2RegImmOp : public ArmStaticInst 181{ 182 protected: 183 IntRegIndex dest, op1, op2; 184 uint64_t imm; 185 186 DataX2RegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 187 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 188 uint64_t _imm) : 189 ArmStaticInst(mnem, _machInst, __opClass), 190 dest(_dest), op1(_op1), op2(_op2), imm(_imm) 191 {} 192
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185 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
| 193 std::string generateDisassembly( 194 Addr pc, const SymbolTable *symtab) const override;
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186}; 187 188class DataX3RegOp : public ArmStaticInst 189{ 190 protected: 191 IntRegIndex dest, op1, op2, op3; 192 193 DataX3RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 194 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 195 IntRegIndex _op3) : 196 ArmStaticInst(mnem, _machInst, __opClass), 197 dest(_dest), op1(_op1), op2(_op2), op3(_op3) 198 {} 199
| 195}; 196 197class DataX3RegOp : public ArmStaticInst 198{ 199 protected: 200 IntRegIndex dest, op1, op2, op3; 201 202 DataX3RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 203 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 204 IntRegIndex _op3) : 205 ArmStaticInst(mnem, _machInst, __opClass), 206 dest(_dest), op1(_op1), op2(_op2), op3(_op3) 207 {} 208
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200 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
| 209 std::string generateDisassembly( 210 Addr pc, const SymbolTable *symtab) const override;
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201}; 202 203class DataXCondCompImmOp : public ArmStaticInst 204{ 205 protected: 206 IntRegIndex op1; 207 uint64_t imm; 208 ConditionCode condCode; 209 uint8_t defCc; 210 211 DataXCondCompImmOp(const char *mnem, ExtMachInst _machInst, 212 OpClass __opClass, IntRegIndex _op1, uint64_t _imm, 213 ConditionCode _condCode, uint8_t _defCc) : 214 ArmStaticInst(mnem, _machInst, __opClass), 215 op1(_op1), imm(_imm), condCode(_condCode), defCc(_defCc) 216 {} 217
| 211}; 212 213class DataXCondCompImmOp : public ArmStaticInst 214{ 215 protected: 216 IntRegIndex op1; 217 uint64_t imm; 218 ConditionCode condCode; 219 uint8_t defCc; 220 221 DataXCondCompImmOp(const char *mnem, ExtMachInst _machInst, 222 OpClass __opClass, IntRegIndex _op1, uint64_t _imm, 223 ConditionCode _condCode, uint8_t _defCc) : 224 ArmStaticInst(mnem, _machInst, __opClass), 225 op1(_op1), imm(_imm), condCode(_condCode), defCc(_defCc) 226 {} 227
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218 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
| 228 std::string generateDisassembly( 229 Addr pc, const SymbolTable *symtab) const override;
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219}; 220 221class DataXCondCompRegOp : public ArmStaticInst 222{ 223 protected: 224 IntRegIndex op1, op2; 225 ConditionCode condCode; 226 uint8_t defCc; 227 228 DataXCondCompRegOp(const char *mnem, ExtMachInst _machInst, 229 OpClass __opClass, IntRegIndex _op1, IntRegIndex _op2, 230 ConditionCode _condCode, uint8_t _defCc) : 231 ArmStaticInst(mnem, _machInst, __opClass), 232 op1(_op1), op2(_op2), condCode(_condCode), defCc(_defCc) 233 {} 234
| 230}; 231 232class DataXCondCompRegOp : public ArmStaticInst 233{ 234 protected: 235 IntRegIndex op1, op2; 236 ConditionCode condCode; 237 uint8_t defCc; 238 239 DataXCondCompRegOp(const char *mnem, ExtMachInst _machInst, 240 OpClass __opClass, IntRegIndex _op1, IntRegIndex _op2, 241 ConditionCode _condCode, uint8_t _defCc) : 242 ArmStaticInst(mnem, _machInst, __opClass), 243 op1(_op1), op2(_op2), condCode(_condCode), defCc(_defCc) 244 {} 245
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235 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
| 246 std::string generateDisassembly( 247 Addr pc, const SymbolTable *symtab) const override;
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236}; 237 238class DataXCondSelOp : public ArmStaticInst 239{ 240 protected: 241 IntRegIndex dest, op1, op2; 242 ConditionCode condCode; 243 244 DataXCondSelOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 245 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 246 ConditionCode _condCode) : 247 ArmStaticInst(mnem, _machInst, __opClass), 248 dest(_dest), op1(_op1), op2(_op2), condCode(_condCode) 249 {} 250
| 248}; 249 250class DataXCondSelOp : public ArmStaticInst 251{ 252 protected: 253 IntRegIndex dest, op1, op2; 254 ConditionCode condCode; 255 256 DataXCondSelOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 257 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 258 ConditionCode _condCode) : 259 ArmStaticInst(mnem, _machInst, __opClass), 260 dest(_dest), op1(_op1), op2(_op2), condCode(_condCode) 261 {} 262
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251 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
| 263 std::string generateDisassembly( 264 Addr pc, const SymbolTable *symtab) const override;
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252}; 253 254} 255 256#endif //__ARCH_ARM_INSTS_PREDINST_HH__
| 265}; 266 267} 268 269#endif //__ARCH_ARM_INSTS_PREDINST_HH__
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