1/*
2 * Copyright (c) 2011-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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50 int64_t imm;
51
52 public:
53 BranchImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
54 int64_t _imm) :
55 ArmStaticInst(mnem, _machInst, __opClass), imm(_imm)
56 {}
57
58 ArmISA::PCState branchTarget(
59 const ArmISA::PCState &branchPC) const override;
60
61 /// Explicitly import the otherwise hidden branchTarget
62 using StaticInst::branchTarget;
63
64 std::string generateDisassembly(
65 Addr pc, const SymbolTable *symtab) const override;
66};
67
68// Conditionally Branch to a target computed with an immediate
69class BranchImmCond64 : public BranchImm64
70{
71 protected:
72 ConditionCode condCode;
73
74 public:
75 BranchImmCond64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
76 int64_t _imm, ConditionCode _condCode) :
77 BranchImm64(mnem, _machInst, __opClass, _imm), condCode(_condCode)
78 {}
79
80 std::string generateDisassembly(
81 Addr pc, const SymbolTable *symtab) const override;
82};
83
84// Branch to a target computed with a register
85class BranchReg64 : public ArmStaticInst
86{
87 protected:
88 IntRegIndex op1;
89
90 public:
91 BranchReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
92 IntRegIndex _op1) :
93 ArmStaticInst(mnem, _machInst, __opClass), op1(_op1)
94 {}
95
96 std::string generateDisassembly(
97 Addr pc, const SymbolTable *symtab) const override;
98};
99
100// Ret instruction
101class BranchRet64 : public BranchReg64
102{
103 public:
104 BranchRet64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
105 IntRegIndex _op1) :
106 BranchReg64(mnem, _machInst, __opClass, _op1)
107 {}
108
109 std::string generateDisassembly(
110 Addr pc, const SymbolTable *symtab) const override;
111};
112
113// Eret instruction
114class BranchEret64 : public ArmStaticInst
115{
116 public:
117 BranchEret64(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
118 ArmStaticInst(mnem, _machInst, __opClass)
119 {}
120
121 std::string generateDisassembly(
122 Addr pc, const SymbolTable *symtab) const override;
123};
124
125// Branch to a target computed with an immediate and a register
126class BranchImmReg64 : public ArmStaticInst
127{
128 protected:
129 int64_t imm;
130 IntRegIndex op1;
131
132 public:
133 BranchImmReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
134 int64_t _imm, IntRegIndex _op1) :
135 ArmStaticInst(mnem, _machInst, __opClass), imm(_imm), op1(_op1)
136 {}
137
138 ArmISA::PCState branchTarget(
139 const ArmISA::PCState &branchPC) const override;
140
141 /// Explicitly import the otherwise hidden branchTarget
142 using StaticInst::branchTarget;
143
144 std::string generateDisassembly(
145 Addr pc, const SymbolTable *symtab) const override;
146};
147
148// Branch to a target computed with two immediates
149class BranchImmImmReg64 : public ArmStaticInst
150{
151 protected:
152 int64_t imm1;
153 int64_t imm2;
154 IntRegIndex op1;
155
156 public:
157 BranchImmImmReg64(const char *mnem, ExtMachInst _machInst,
158 OpClass __opClass, int64_t _imm1, int64_t _imm2,
159 IntRegIndex _op1) :
160 ArmStaticInst(mnem, _machInst, __opClass),
161 imm1(_imm1), imm2(_imm2), op1(_op1)
162 {}
163
164 ArmISA::PCState branchTarget(
165 const ArmISA::PCState &branchPC) const override;
166
167 /// Explicitly import the otherwise hidden branchTarget
168 using StaticInst::branchTarget;
169
170 std::string generateDisassembly(
171 Addr pc, const SymbolTable *symtab) const override;
172};
173
174}
175
176#endif //__ARCH_ARM_INSTS_BRANCH_HH__