faults.hh (8591:8f23aeaf6a91) faults.hh (8782:10c9297e14d5)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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43 */
44
45#ifndef __ARM_FAULTS_HH__
46#define __ARM_FAULTS_HH__
47
48#include "arch/arm/miscregs.hh"
49#include "arch/arm/types.hh"
50#include "base/misc.hh"
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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43 */
44
45#ifndef __ARM_FAULTS_HH__
46#define __ARM_FAULTS_HH__
47
48#include "arch/arm/miscregs.hh"
49#include "arch/arm/types.hh"
50#include "base/misc.hh"
51#include "config/full_system.hh"
52#include "sim/faults.hh"
51#include "sim/faults.hh"
52#include "sim/full_system.hh"
53
54// The design of the "name" and "vect" functions is in sim/faults.hh
55
56namespace ArmISA
57{
58typedef const Addr FaultOffset;
59
60class ArmFault : public FaultBase

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103 const OperatingMode nextMode;
104 const uint8_t armPcOffset;
105 const uint8_t thumbPcOffset;
106 const bool abortDisable;
107 const bool fiqDisable;
108 FaultStat count;
109 };
110
53
54// The design of the "name" and "vect" functions is in sim/faults.hh
55
56namespace ArmISA
57{
58typedef const Addr FaultOffset;
59
60class ArmFault : public FaultBase

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103 const OperatingMode nextMode;
104 const uint8_t armPcOffset;
105 const uint8_t thumbPcOffset;
106 const bool abortDisable;
107 const bool fiqDisable;
108 FaultStat count;
109 };
110
111#if FULL_SYSTEM
112 void invoke(ThreadContext *tc,
113 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
111 void invoke(ThreadContext *tc,
112 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
114#endif
115 virtual FaultStat& countStat() = 0;
116 virtual FaultOffset offset() = 0;
117 virtual OperatingMode nextMode() = 0;
118 virtual uint8_t armPcOffset() = 0;
119 virtual uint8_t thumbPcOffset() = 0;
120 virtual bool abortDisable() = 0;
121 virtual bool fiqDisable() = 0;
122};

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134 OperatingMode nextMode() { return vals.nextMode; }
135 uint8_t armPcOffset() { return vals.armPcOffset; }
136 uint8_t thumbPcOffset() { return vals.thumbPcOffset; }
137 bool abortDisable() { return vals.abortDisable; }
138 bool fiqDisable() { return vals.fiqDisable; }
139};
140
141class Reset : public ArmFaultVals<Reset>
113 virtual FaultStat& countStat() = 0;
114 virtual FaultOffset offset() = 0;
115 virtual OperatingMode nextMode() = 0;
116 virtual uint8_t armPcOffset() = 0;
117 virtual uint8_t thumbPcOffset() = 0;
118 virtual bool abortDisable() = 0;
119 virtual bool fiqDisable() = 0;
120};

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132 OperatingMode nextMode() { return vals.nextMode; }
133 uint8_t armPcOffset() { return vals.armPcOffset; }
134 uint8_t thumbPcOffset() { return vals.thumbPcOffset; }
135 bool abortDisable() { return vals.abortDisable; }
136 bool fiqDisable() { return vals.fiqDisable; }
137};
138
139class Reset : public ArmFaultVals<Reset>
142#if FULL_SYSTEM
143{
144 public:
145 void invoke(ThreadContext *tc,
146 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
147};
140{
141 public:
142 void invoke(ThreadContext *tc,
143 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
144};
148#else
149{};
150#endif //FULL_SYSTEM
151
152class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
153{
145
146class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
147{
154#if !FULL_SYSTEM
155 protected:
156 ExtMachInst machInst;
157 bool unknown;
158 const char *mnemonic;
159 bool disabled;
160
161 public:
162 UndefinedInstruction(ExtMachInst _machInst,
163 bool _unknown,
164 const char *_mnemonic = NULL,
165 bool _disabled = false) :
166 machInst(_machInst), unknown(_unknown),
167 mnemonic(_mnemonic), disabled(_disabled)
168 {
169 }
148 protected:
149 ExtMachInst machInst;
150 bool unknown;
151 const char *mnemonic;
152 bool disabled;
153
154 public:
155 UndefinedInstruction(ExtMachInst _machInst,
156 bool _unknown,
157 const char *_mnemonic = NULL,
158 bool _disabled = false) :
159 machInst(_machInst), unknown(_unknown),
160 mnemonic(_mnemonic), disabled(_disabled)
161 {
162 }
163 UndefinedInstruction() :
164 machInst(0), unknown(false), mnemonic("undefined"), disabled(false)
165 {}
170
171 void invoke(ThreadContext *tc,
172 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
166
167 void invoke(ThreadContext *tc,
168 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
173#endif
174};
175
176class SupervisorCall : public ArmFaultVals<SupervisorCall>
177{
169};
170
171class SupervisorCall : public ArmFaultVals<SupervisorCall>
172{
178#if !FULL_SYSTEM
179 protected:
180 ExtMachInst machInst;
181
182 public:
183 SupervisorCall(ExtMachInst _machInst) : machInst(_machInst)
184 {}
173 protected:
174 ExtMachInst machInst;
175
176 public:
177 SupervisorCall(ExtMachInst _machInst) : machInst(_machInst)
178 {}
179 SupervisorCall() : machInst(0)
180 {}
185
186 void invoke(ThreadContext *tc,
187 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
181
182 void invoke(ThreadContext *tc,
183 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
188#endif
189};
190
191template <class T>
192class AbortFault : public ArmFaultVals<T>
193{
194 protected:
195 Addr faultAddr;
196 bool write;

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185
186template <class T>
187class AbortFault : public ArmFaultVals<T>
188{
189 protected:
190 Addr faultAddr;
191 bool write;

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