faults.hh (7652:f2621206b062) | faults.hh (7678:f19b6a3a8cec) |
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1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 94 unchanged lines hidden (view full) --- 103 const uint8_t armPcOffset; 104 const uint8_t thumbPcOffset; 105 const bool abortDisable; 106 const bool fiqDisable; 107 FaultStat count; 108 }; 109 110#if FULL_SYSTEM | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 94 unchanged lines hidden (view full) --- 103 const uint8_t armPcOffset; 104 const uint8_t thumbPcOffset; 105 const bool abortDisable; 106 const bool fiqDisable; 107 FaultStat count; 108 }; 109 110#if FULL_SYSTEM |
111 void invoke(ThreadContext *tc); | 111 void invoke(ThreadContext *tc, 112 StaticInstPtr inst = StaticInst::nullStaticInstPtr); |
112#endif 113 virtual FaultStat& countStat() = 0; 114 virtual FaultOffset offset() = 0; 115 virtual OperatingMode nextMode() = 0; 116 virtual uint8_t armPcOffset() = 0; 117 virtual uint8_t thumbPcOffset() = 0; 118 virtual bool abortDisable() = 0; 119 virtual bool fiqDisable() = 0; --- 15 unchanged lines hidden (view full) --- 135 bool abortDisable() { return vals.abortDisable; } 136 bool fiqDisable() { return vals.fiqDisable; } 137}; 138 139class Reset : public ArmFaultVals<Reset> 140#if FULL_SYSTEM 141{ 142 public: | 113#endif 114 virtual FaultStat& countStat() = 0; 115 virtual FaultOffset offset() = 0; 116 virtual OperatingMode nextMode() = 0; 117 virtual uint8_t armPcOffset() = 0; 118 virtual uint8_t thumbPcOffset() = 0; 119 virtual bool abortDisable() = 0; 120 virtual bool fiqDisable() = 0; --- 15 unchanged lines hidden (view full) --- 136 bool abortDisable() { return vals.abortDisable; } 137 bool fiqDisable() { return vals.fiqDisable; } 138}; 139 140class Reset : public ArmFaultVals<Reset> 141#if FULL_SYSTEM 142{ 143 public: |
143 void invoke(ThreadContext *tc); | 144 void invoke(ThreadContext *tc, 145 StaticInstPtr inst = StaticInst::nullStaticInstPtr); |
144}; 145#else 146{}; 147#endif //FULL_SYSTEM 148 149class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction> 150{ 151#if !FULL_SYSTEM --- 8 unchanged lines hidden (view full) --- 160 bool _unknown, 161 const char *_mnemonic = NULL, 162 bool _disabled = false) : 163 machInst(_machInst), unknown(_unknown), 164 mnemonic(_mnemonic), disabled(_disabled) 165 { 166 } 167 | 146}; 147#else 148{}; 149#endif //FULL_SYSTEM 150 151class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction> 152{ 153#if !FULL_SYSTEM --- 8 unchanged lines hidden (view full) --- 162 bool _unknown, 163 const char *_mnemonic = NULL, 164 bool _disabled = false) : 165 machInst(_machInst), unknown(_unknown), 166 mnemonic(_mnemonic), disabled(_disabled) 167 { 168 } 169 |
168 void invoke(ThreadContext *tc); | 170 void invoke(ThreadContext *tc, 171 StaticInstPtr inst = StaticInst::nullStaticInstPtr); |
169#endif 170}; 171 172class SupervisorCall : public ArmFaultVals<SupervisorCall> 173{ 174#if !FULL_SYSTEM 175 protected: 176 ExtMachInst machInst; 177 178 public: 179 SupervisorCall(ExtMachInst _machInst) : machInst(_machInst) 180 {} 181 | 172#endif 173}; 174 175class SupervisorCall : public ArmFaultVals<SupervisorCall> 176{ 177#if !FULL_SYSTEM 178 protected: 179 ExtMachInst machInst; 180 181 public: 182 SupervisorCall(ExtMachInst _machInst) : machInst(_machInst) 183 {} 184 |
182 void invoke(ThreadContext *tc); | 185 void invoke(ThreadContext *tc, 186 StaticInstPtr inst = StaticInst::nullStaticInstPtr); |
183#endif 184}; 185 186template <class T> 187class AbortFault : public ArmFaultVals<T> 188{ 189 protected: 190 Addr faultAddr; 191 bool write; 192 uint8_t domain; 193 uint8_t status; 194 195 public: 196 AbortFault(Addr _faultAddr, bool _write, 197 uint8_t _domain, uint8_t _status) : 198 faultAddr(_faultAddr), write(_write), 199 domain(_domain), status(_status) 200 {} 201 | 187#endif 188}; 189 190template <class T> 191class AbortFault : public ArmFaultVals<T> 192{ 193 protected: 194 Addr faultAddr; 195 bool write; 196 uint8_t domain; 197 uint8_t status; 198 199 public: 200 AbortFault(Addr _faultAddr, bool _write, 201 uint8_t _domain, uint8_t _status) : 202 faultAddr(_faultAddr), write(_write), 203 domain(_domain), status(_status) 204 {} 205 |
202 void invoke(ThreadContext *tc); | 206 void invoke(ThreadContext *tc, 207 StaticInstPtr inst = StaticInst::nullStaticInstPtr); |
203}; 204 205class PrefetchAbort : public AbortFault<PrefetchAbort> 206{ 207 public: 208 static const MiscRegIndex FsrIndex = MISCREG_IFSR; 209 static const MiscRegIndex FarIndex = MISCREG_IFAR; 210 --- 16 unchanged lines hidden (view full) --- 227class Interrupt : public ArmFaultVals<Interrupt> {}; 228class FastInterrupt : public ArmFaultVals<FastInterrupt> {}; 229 230// A fault that flushes the pipe, excluding the faulting instructions 231class FlushPipe : public ArmFaultVals<FlushPipe> 232{ 233 public: 234 FlushPipe() {} | 208}; 209 210class PrefetchAbort : public AbortFault<PrefetchAbort> 211{ 212 public: 213 static const MiscRegIndex FsrIndex = MISCREG_IFSR; 214 static const MiscRegIndex FarIndex = MISCREG_IFAR; 215 --- 16 unchanged lines hidden (view full) --- 232class Interrupt : public ArmFaultVals<Interrupt> {}; 233class FastInterrupt : public ArmFaultVals<FastInterrupt> {}; 234 235// A fault that flushes the pipe, excluding the faulting instructions 236class FlushPipe : public ArmFaultVals<FlushPipe> 237{ 238 public: 239 FlushPipe() {} |
235 void invoke(ThreadContext *tc); | 240 void invoke(ThreadContext *tc, 241 StaticInstPtr inst = StaticInst::nullStaticInstPtr); |
236}; 237 238static inline Fault genMachineCheckFault() 239{ 240 return new Reset(); 241} 242 243} // ArmISA namespace 244 245#endif // __ARM_FAULTS_HH__ | 242}; 243 244static inline Fault genMachineCheckFault() 245{ 246 return new Reset(); 247} 248 249} // ArmISA namespace 250 251#endif // __ARM_FAULTS_HH__ |