faults.hh (7197:21b9790c446d) | faults.hh (7362:9ea92e0eb4a9) |
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1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 31 unchanged lines hidden (view full) --- 40 * 41 * Authors: Ali Saidi 42 * Gabe Black 43 */ 44 45#ifndef __ARM_FAULTS_HH__ 46#define __ARM_FAULTS_HH__ 47 | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 31 unchanged lines hidden (view full) --- 40 * 41 * Authors: Ali Saidi 42 * Gabe Black 43 */ 44 45#ifndef __ARM_FAULTS_HH__ 46#define __ARM_FAULTS_HH__ 47 |
48#include "arch/arm/miscregs.hh" |
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48#include "arch/arm/types.hh" 49#include "config/full_system.hh" 50#include "sim/faults.hh" 51 52// The design of the "name" and "vect" functions is in sim/faults.hh 53 54namespace ArmISA 55{ 56typedef const Addr FaultOffset; 57 | 49#include "arch/arm/types.hh" 50#include "config/full_system.hh" 51#include "sim/faults.hh" 52 53// The design of the "name" and "vect" functions is in sim/faults.hh 54 55namespace ArmISA 56{ 57typedef const Addr FaultOffset; 58 |
58class ArmFaultBase : public FaultBase | 59class ArmFault : public FaultBase |
59{ 60 protected: 61 Addr getVector(ThreadContext *tc); 62 63 public: | 60{ 61 protected: 62 Addr getVector(ThreadContext *tc); 63 64 public: |
65 enum StatusEncoding 66 { 67 // Fault Status register encodings 68 // ARM ARM B3.9.4 69 AlignmentFault = 0x1, 70 DebugEvent = 0x2, 71 AccessFlag0 = 0x3, 72 InstructionCacheMaintenance = 0x4, 73 Translation0 = 0x5, 74 AccessFlag1 = 0x6, 75 Translation1 = 0x7, 76 SynchronousExternalAbort0 = 0x8, 77 Domain0 = 0x9, 78 Domain1 = 0xb, 79 TranslationTableWalk0 = 0xc, 80 Permission0 = 0xd, 81 SynchronousExternalAbort1 = 0xe, 82 Permission1 = 0xf, 83 AsynchronousExternalAbort = 0x16, 84 MemoryAccessAsynchronousParityError = 0x18, 85 MemoryAccessSynchronousParityError = 0x19, 86 TranslationTableWalk1 = 0x1c, 87 SynchronousParityError = 0x1e 88 }; 89 |
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64 struct FaultVals 65 { 66 const FaultName name; 67 const FaultOffset offset; 68 const OperatingMode nextMode; 69 const uint8_t armPcOffset; 70 const uint8_t thumbPcOffset; 71 const bool abortDisable; --- 9 unchanged lines hidden (view full) --- 81 virtual OperatingMode nextMode() = 0; 82 virtual uint8_t armPcOffset() = 0; 83 virtual uint8_t thumbPcOffset() = 0; 84 virtual bool abortDisable() = 0; 85 virtual bool fiqDisable() = 0; 86}; 87 88template<typename T> | 90 struct FaultVals 91 { 92 const FaultName name; 93 const FaultOffset offset; 94 const OperatingMode nextMode; 95 const uint8_t armPcOffset; 96 const uint8_t thumbPcOffset; 97 const bool abortDisable; --- 9 unchanged lines hidden (view full) --- 107 virtual OperatingMode nextMode() = 0; 108 virtual uint8_t armPcOffset() = 0; 109 virtual uint8_t thumbPcOffset() = 0; 110 virtual bool abortDisable() = 0; 111 virtual bool fiqDisable() = 0; 112}; 113 114template<typename T> |
89class ArmFault : public ArmFaultBase | 115class ArmFaultVals : public ArmFault |
90{ 91 protected: 92 static FaultVals vals; 93 94 public: 95 FaultName name() const { return vals.name; } 96 FaultStat & countStat() {return vals.count;} 97 FaultOffset offset() { return vals.offset; } 98 OperatingMode nextMode() { return vals.nextMode; } 99 uint8_t armPcOffset() { return vals.armPcOffset; } 100 uint8_t thumbPcOffset() { return vals.thumbPcOffset; } 101 bool abortDisable() { return vals.abortDisable; } 102 bool fiqDisable() { return vals.fiqDisable; } 103}; 104 105 | 116{ 117 protected: 118 static FaultVals vals; 119 120 public: 121 FaultName name() const { return vals.name; } 122 FaultStat & countStat() {return vals.count;} 123 FaultOffset offset() { return vals.offset; } 124 OperatingMode nextMode() { return vals.nextMode; } 125 uint8_t armPcOffset() { return vals.armPcOffset; } 126 uint8_t thumbPcOffset() { return vals.thumbPcOffset; } 127 bool abortDisable() { return vals.abortDisable; } 128 bool fiqDisable() { return vals.fiqDisable; } 129}; 130 131 |
106class Reset : public ArmFault<Reset> {}; | 132class Reset : public ArmFaultVals<Reset> {}; |
107 | 133 |
108class UndefinedInstruction : public ArmFault | 134class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction> |
109{ 110#if !FULL_SYSTEM 111 protected: 112 ExtMachInst machInst; 113 bool unknown; 114 const char *mnemonic; 115 116 public: 117 UndefinedInstruction(ExtMachInst _machInst, 118 bool _unknown, 119 const char *_mnemonic = NULL) : 120 machInst(_machInst), unknown(_unknown), mnemonic(_mnemonic) 121 { 122 } 123 124 void invoke(ThreadContext *tc); 125#endif 126}; 127 | 135{ 136#if !FULL_SYSTEM 137 protected: 138 ExtMachInst machInst; 139 bool unknown; 140 const char *mnemonic; 141 142 public: 143 UndefinedInstruction(ExtMachInst _machInst, 144 bool _unknown, 145 const char *_mnemonic = NULL) : 146 machInst(_machInst), unknown(_unknown), mnemonic(_mnemonic) 147 { 148 } 149 150 void invoke(ThreadContext *tc); 151#endif 152}; 153 |
128class SupervisorCall : public ArmFault<SupervisorCall> | 154class SupervisorCall : public ArmFaultVals<SupervisorCall> |
129{ 130#if !FULL_SYSTEM 131 protected: 132 ExtMachInst machInst; 133 134 public: 135 SupervisorCall(ExtMachInst _machInst) : machInst(_machInst) 136 {} 137 138 void invoke(ThreadContext *tc); 139#endif 140}; | 155{ 156#if !FULL_SYSTEM 157 protected: 158 ExtMachInst machInst; 159 160 public: 161 SupervisorCall(ExtMachInst _machInst) : machInst(_machInst) 162 {} 163 164 void invoke(ThreadContext *tc); 165#endif 166}; |
141class PrefetchAbort : public ArmFault<PrefetchAbort> {}; 142class DataAbort : public ArmFault<DataAbort> {}; 143class Interrupt : public ArmFault<Interrupt> {}; 144class FastInterrupt : public ArmFault<FastInterrupt> {}; | |
145 | 167 |
168template <class T> 169class AbortFault : public ArmFaultVals<T> 170{ 171 protected: 172 Addr faultAddr; 173 bool write; 174 uint8_t domain; 175 uint8_t status; |
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146 | 176 |
177 public: 178 AbortFault(Addr _faultAddr, bool _write, 179 uint8_t _domain, uint8_t _status) : 180 faultAddr(_faultAddr), write(_write), 181 domain(_domain), status(_status) 182 {} 183 184 void invoke(ThreadContext *tc); 185}; 186 187class PrefetchAbort : public AbortFault<PrefetchAbort> 188{ 189 public: 190 static const MiscRegIndex FsrIndex = MISCREG_IFSR; 191 static const MiscRegIndex FarIndex = MISCREG_IFAR; 192 193 PrefetchAbort(Addr _addr, uint8_t _status) : 194 AbortFault<PrefetchAbort>(_addr, false, 0, _status) 195 {} 196}; 197 198class DataAbort : public AbortFault<DataAbort> 199{ 200 public: 201 static const MiscRegIndex FsrIndex = MISCREG_DFSR; 202 static const MiscRegIndex FarIndex = MISCREG_DFAR; 203 204 DataAbort(Addr _addr, bool _write, uint8_t _domain, uint8_t _status) : 205 AbortFault<DataAbort>(_addr, _write, _domain, _status) 206 {} 207}; 208 209class Interrupt : public ArmFaultVals<Interrupt> {}; 210class FastInterrupt : public ArmFaultVals<FastInterrupt> {}; 211 212 |
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147} // ArmISA namespace 148 149#endif // __ARM_FAULTS_HH__ | 213} // ArmISA namespace 214 215#endif // __ARM_FAULTS_HH__ |