faults.hh (12569:fe1ff4059715) faults.hh (12570:e32771e88250)
1/*
2 * Copyright (c) 2010, 2012-2013, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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223 virtual uint8_t thumbPcOffset(bool isHyp) = 0;
224 virtual uint8_t armPcElrOffset() = 0;
225 virtual uint8_t thumbPcElrOffset() = 0;
226 virtual bool abortDisable(ThreadContext *tc) = 0;
227 virtual bool fiqDisable(ThreadContext *tc) = 0;
228 virtual ExceptionClass ec(ThreadContext *tc) const = 0;
229 virtual uint32_t iss() const = 0;
230 virtual bool isStage2() const { return false; }
1/*
2 * Copyright (c) 2010, 2012-2013, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 214 unchanged lines hidden (view full) ---

223 virtual uint8_t thumbPcOffset(bool isHyp) = 0;
224 virtual uint8_t armPcElrOffset() = 0;
225 virtual uint8_t thumbPcElrOffset() = 0;
226 virtual bool abortDisable(ThreadContext *tc) = 0;
227 virtual bool fiqDisable(ThreadContext *tc) = 0;
228 virtual ExceptionClass ec(ThreadContext *tc) const = 0;
229 virtual uint32_t iss() const = 0;
230 virtual bool isStage2() const { return false; }
231 virtual FSR getFsr(ThreadContext *tc) { return 0; }
231 virtual FSR getFsr(ThreadContext *tc) const { return 0; }
232 virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg);
233};
234
235template<typename T>
236class ArmFaultVals : public ArmFault
237{
238 protected:
239 static FaultVals vals;

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426 faultAddr(_faultAddr), OVAddr(0), write(_write),
427 domain(_domain), source(_source), srcEncoded(0),
428 stage2(_stage2), s1ptw(false), tranMethod(_tranMethod)
429 {}
430
431 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
432 StaticInst::nullStaticInstPtr) override;
433
232 virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg);
233};
234
235template<typename T>
236class ArmFaultVals : public ArmFault
237{
238 protected:
239 static FaultVals vals;

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426 faultAddr(_faultAddr), OVAddr(0), write(_write),
427 domain(_domain), source(_source), srcEncoded(0),
428 stage2(_stage2), s1ptw(false), tranMethod(_tranMethod)
429 {}
430
431 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
432 StaticInst::nullStaticInstPtr) override;
433
434 FSR getFsr(ThreadContext *tc) override;
434 FSR getFsr(ThreadContext *tc) const override;
435 uint8_t getFaultStatusCode(ThreadContext *tc) const;
435 bool abortDisable(ThreadContext *tc) override;
436 uint32_t iss() const override;
437 bool isStage2() const override { return stage2; }
438 void annotate(ArmFault::AnnotationIDs id, uint64_t val) override;
436 bool abortDisable(ThreadContext *tc) override;
437 uint32_t iss() const override;
438 bool isStage2() const override { return stage2; }
439 void annotate(ArmFault::AnnotationIDs id, uint64_t val) override;
440 void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) override;
439 bool isMMUFault() const;
440};
441
442class PrefetchAbort : public AbortFault<PrefetchAbort>
443{
444 public:
445 static const MiscRegIndex FsrIndex = MISCREG_IFSR;
446 static const MiscRegIndex FarIndex = MISCREG_IFAR;

--- 174 unchanged lines hidden --- 		441 bool isMMUFault() const;
442};
443
444class PrefetchAbort : public AbortFault<PrefetchAbort>
445{
446 public:
447 static const MiscRegIndex FsrIndex = MISCREG_IFSR;
448 static const MiscRegIndex FarIndex = MISCREG_IFAR;

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