faults.hh (10417:710ee116eb68) faults.hh (10537:47fe87b0cf97)
1/*
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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167 // Exception class used to appropriately set the syndrome register
168 // (exceptions taken in HYP mode or in AArch64 state)
169 const ExceptionClass ec;
170
171 FaultStat count;
172 };
173
174 ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
1/*
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 158 unchanged lines hidden (view full) ---

167 // Exception class used to appropriately set the syndrome register
168 // (exceptions taken in HYP mode or in AArch64 state)
169 const ExceptionClass ec;
170
171 FaultStat count;
172 };
173
174 ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
175 machInst(_machInst), issRaw(_iss), from64(false), to64(false) {}
175 machInst(_machInst), issRaw(_iss), from64(false), to64(false),
176 fromEL(EL0), toEL(EL0), fromMode(MODE_UNDEFINED) {}
176
177 // Returns the actual syndrome register to use based on the target
178 // exception level
179 MiscRegIndex getSyndromeReg64() const;
180 // Returns the actual fault address register to use based on the target
181 // exception level
182 MiscRegIndex getFaultAddrReg64() const;
183

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390 TlbEntry::DomainType domain;
391 uint8_t source;
392 uint8_t srcEncoded;
393 bool stage2;
394 bool s1ptw;
395 ArmFault::TranMethod tranMethod;
396
397 public:
177
178 // Returns the actual syndrome register to use based on the target
179 // exception level
180 MiscRegIndex getSyndromeReg64() const;
181 // Returns the actual fault address register to use based on the target
182 // exception level
183 MiscRegIndex getFaultAddrReg64() const;
184

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391 TlbEntry::DomainType domain;
392 uint8_t source;
393 uint8_t srcEncoded;
394 bool stage2;
395 bool s1ptw;
396 ArmFault::TranMethod tranMethod;
397
398 public:
398 AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain, uint8_t _source,
399 bool _stage2, ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) :
400 faultAddr(_faultAddr), write(_write), domain(_domain), source(_source),
399 AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain,
400 uint8_t _source, bool _stage2,
401 ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) :
402 faultAddr(_faultAddr), OVAddr(0), write(_write),
403 domain(_domain), source(_source), srcEncoded(0),
401 stage2(_stage2), s1ptw(false), tranMethod(_tranMethod)
402 {}
403
404 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
405 StaticInst::nullStaticInstPtr);
406
407 FSR getFsr(ThreadContext *tc);
408 bool abortDisable(ThreadContext *tc);

--- 158 unchanged lines hidden --- 		404 stage2(_stage2), s1ptw(false), tranMethod(_tranMethod)
405 {}
406
407 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
408 StaticInst::nullStaticInstPtr);
409
410 FSR getFsr(ThreadContext *tc);
411 bool abortDisable(ThreadContext *tc);

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