1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 35 unchanged lines hidden (view full) --- 44 45#ifndef __ARM_FAULTS_HH__ 46#define __ARM_FAULTS_HH__ 47 48#include "arch/arm/miscregs.hh" 49#include "arch/arm/types.hh" 50#include "config/full_system.hh" 51#include "sim/faults.hh" |
52#include "base/misc.hh" |
53 54// The design of the "name" and "vect" functions is in sim/faults.hh 55 56namespace ArmISA 57{ 58typedef const Addr FaultOffset; 59 60class ArmFault : public FaultBase --- 152 unchanged lines hidden (view full) --- 213 DataAbort(Addr _addr, uint8_t _domain, bool _write, uint8_t _status) : 214 AbortFault<DataAbort>(_addr, _write, _domain, _status) 215 {} 216}; 217 218class Interrupt : public ArmFaultVals<Interrupt> {}; 219class FastInterrupt : public ArmFaultVals<FastInterrupt> {}; 220 |
221static inline Fault genMachineCheckFault() 222{ 223 return new Reset(); 224} |
225 226} // ArmISA namespace 227 228#endif // __ARM_FAULTS_HH__ |