1/*
| 1/*
|
2 * Copyright (c) 2010 ARM Limited
| 2 * Copyright (c) 2010, 2012-2013 ARM Limited
|
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * Copyright (c) 2007-2008 The Florida State University 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Ali Saidi 42 * Gabe Black
| 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * Copyright (c) 2007-2008 The Florida State University 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Ali Saidi 42 * Gabe Black
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| 43 * Giacomo Gabrielli 44 * Thomas Grocutt
|
43 */ 44 45#ifndef __ARM_FAULTS_HH__ 46#define __ARM_FAULTS_HH__ 47 48#include "arch/arm/miscregs.hh"
| 45 */ 46 47#ifndef __ARM_FAULTS_HH__ 48#define __ARM_FAULTS_HH__ 49 50#include "arch/arm/miscregs.hh"
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| 51#include "arch/arm/pagetable.hh"
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49#include "arch/arm/types.hh" 50#include "base/misc.hh" 51#include "sim/faults.hh" 52#include "sim/full_system.hh" 53 54// The design of the "name" and "vect" functions is in sim/faults.hh 55 56namespace ArmISA 57{ 58typedef const Addr FaultOffset; 59 60class ArmFault : public FaultBase 61{ 62 protected:
| 52#include "arch/arm/types.hh" 53#include "base/misc.hh" 54#include "sim/faults.hh" 55#include "sim/full_system.hh" 56 57// The design of the "name" and "vect" functions is in sim/faults.hh 58 59namespace ArmISA 60{ 61typedef const Addr FaultOffset; 62 63class ArmFault : public FaultBase 64{ 65 protected:
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| 66 ExtMachInst machInst; 67 uint32_t issRaw; 68 69 // Helper variables for ARMv8 exception handling 70 bool from64; // True if the exception is generated from the AArch64 state 71 bool to64; // True if the exception is taken in AArch64 state 72 ExceptionLevel fromEL; // Source exception level 73 ExceptionLevel toEL; // Target exception level 74 OperatingMode fromMode; // Source operating mode 75
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63 Addr getVector(ThreadContext *tc);
| 76 Addr getVector(ThreadContext *tc);
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| 77 Addr getVector64(ThreadContext *tc);
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64 65 public:
| 78 79 public:
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66 enum StatusEncoding
| 80 /// Generic fault source enums used to index into 81 /// {short/long/aarch64}DescFaultSources[] to get the actual encodings based 82 /// on the current register width state and the translation table format in 83 /// use 84 enum FaultSource
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67 {
| 85 {
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68 // Fault Status register encodings 69 // ARM ARM B3.9.4 70 AlignmentFault = 0x1, 71 DebugEvent = 0x2, 72 AccessFlag0 = 0x3, 73 InstructionCacheMaintenance = 0x4, 74 Translation0 = 0x5, 75 AccessFlag1 = 0x6, 76 Translation1 = 0x7, 77 SynchronousExternalAbort0 = 0x8, 78 Domain0 = 0x9, 79 SynchronousExternalAbort1 = 0x8, 80 Domain1 = 0xb, 81 TranslationTableWalkExtAbt0 = 0xc, 82 Permission0 = 0xd, 83 TranslationTableWalkExtAbt1 = 0xe, 84 Permission1 = 0xf, 85 AsynchronousExternalAbort = 0x16, 86 MemoryAccessAsynchronousParityError = 0x18, 87 MemoryAccessSynchronousParityError = 0x19, 88 TranslationTableWalkPrtyErr0 = 0x1c, 89 TranslationTableWalkPrtyErr1 = 0x1e,
| 86 AlignmentFault = 0, 87 InstructionCacheMaintenance, // Short-desc. format only 88 SynchExtAbtOnTranslTableWalkLL, 89 SynchPtyErrOnTranslTableWalkLL = SynchExtAbtOnTranslTableWalkLL + 4, 90 TranslationLL = SynchPtyErrOnTranslTableWalkLL + 4, 91 AccessFlagLL = TranslationLL + 4, 92 DomainLL = AccessFlagLL + 4, 93 PermissionLL = DomainLL + 4, 94 DebugEvent = PermissionLL + 4, 95 SynchronousExternalAbort, 96 TLBConflictAbort, // Requires LPAE 97 SynchPtyErrOnMemoryAccess, 98 AsynchronousExternalAbort, 99 AsynchPtyErrOnMemoryAccess, 100 AddressSizeLL, // AArch64 only
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90
| 101
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91 // not a real fault. This is a status code 92 // to allow the translation function to inform 93 // the memory access function not to proceed 94 // for a Prefetch that misses in the TLB. 95 PrefetchTLBMiss = 0x1f, 96 PrefetchUncacheable = 0x20
| 102 // Not real faults. These are faults to allow the translation function 103 // to inform the memory access function not to proceed for a prefetch 104 // that misses in the TLB or that targets an uncacheable address 105 PrefetchTLBMiss = AddressSizeLL + 4, 106 PrefetchUncacheable, 107 108 NumFaultSources, 109 FaultSourceInvalid = 0xff
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97 }; 98
| 110 }; 111
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| 112 /// Encodings of the fault sources when the short-desc. translation table 113 /// format is in use (ARM ARM Issue C B3.13.3) 114 static uint8_t shortDescFaultSources[NumFaultSources]; 115 /// Encodings of the fault sources when the long-desc. translation table 116 /// format is in use (ARM ARM Issue C B3.13.3) 117 static uint8_t longDescFaultSources[NumFaultSources]; 118 /// Encodings of the fault sources in AArch64 state 119 static uint8_t aarch64FaultSources[NumFaultSources]; 120 121 enum AnnotationIDs 122 { 123 S1PTW, // DataAbort, PrefetchAbort: Stage 1 Page Table Walk, 124 OVA, // DataAbort, PrefetchAbort: stage 1 Virtual Address for stage 2 faults 125 SAS, // DataAbort: Syndrome Access Size 126 SSE, // DataAbort: Syndrome Sign Extend 127 SRT, // DataAbort: Syndrome Register Transfer 128 129 // AArch64 only 130 SF, // DataAbort: width of the accessed register is SixtyFour 131 AR // DataAbort: Acquire/Release semantics 132 }; 133 134 enum TranMethod 135 { 136 LpaeTran, 137 VmsaTran, 138 UnknownTran 139 }; 140
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99 struct FaultVals 100 { 101 const FaultName name;
| 141 struct FaultVals 142 { 143 const FaultName name;
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| 144
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102 const FaultOffset offset;
| 145 const FaultOffset offset;
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| 146 147 // Offsets used for exceptions taken in AArch64 state 148 const uint16_t currELTOffset; 149 const uint16_t currELHOffset; 150 const uint16_t lowerEL64Offset; 151 const uint16_t lowerEL32Offset; 152
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103 const OperatingMode nextMode;
| 153 const OperatingMode nextMode;
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| 154
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104 const uint8_t armPcOffset; 105 const uint8_t thumbPcOffset;
| 155 const uint8_t armPcOffset; 156 const uint8_t thumbPcOffset;
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| 157 // The following two values are used in place of armPcOffset and 158 // thumbPcOffset when the exception return address is saved into ELR 159 // registers (exceptions taken in HYP mode or in AArch64 state) 160 const uint8_t armPcElrOffset; 161 const uint8_t thumbPcElrOffset; 162 163 const bool hypTrappable;
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106 const bool abortDisable; 107 const bool fiqDisable;
| 164 const bool abortDisable; 165 const bool fiqDisable;
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| 166 167 // Exception class used to appropriately set the syndrome register 168 // (exceptions taken in HYP mode or in AArch64 state) 169 const ExceptionClass ec; 170
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108 FaultStat count; 109 }; 110
| 171 FaultStat count; 172 }; 173
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| 174 ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) : 175 machInst(_machInst), issRaw(_iss), from64(false), to64(false) {} 176 177 // Returns the actual syndrome register to use based on the target 178 // exception level 179 MiscRegIndex getSyndromeReg64() const; 180 // Returns the actual fault address register to use based on the target 181 // exception level 182 MiscRegIndex getFaultAddrReg64() const; 183
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111 void invoke(ThreadContext *tc, 112 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
| 184 void invoke(ThreadContext *tc, 185 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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| 186 void invoke64(ThreadContext *tc, 187 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 188 virtual void annotate(AnnotationIDs id, uint64_t val) {}
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113 virtual FaultStat& countStat() = 0;
| 189 virtual FaultStat& countStat() = 0;
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114 virtual FaultOffset offset() = 0;
| 190 virtual FaultOffset offset(ThreadContext *tc) = 0; 191 virtual FaultOffset offset64() = 0;
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115 virtual OperatingMode nextMode() = 0;
| 192 virtual OperatingMode nextMode() = 0;
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116 virtual uint8_t armPcOffset() = 0; 117 virtual uint8_t thumbPcOffset() = 0; 118 virtual bool abortDisable() = 0; 119 virtual bool fiqDisable() = 0;
| 193 virtual bool routeToMonitor(ThreadContext *tc) const = 0; 194 virtual bool routeToHyp(ThreadContext *tc) const { return false; } 195 virtual uint8_t armPcOffset(bool isHyp) = 0; 196 virtual uint8_t thumbPcOffset(bool isHyp) = 0; 197 virtual uint8_t armPcElrOffset() = 0; 198 virtual uint8_t thumbPcElrOffset() = 0; 199 virtual bool abortDisable(ThreadContext *tc) = 0; 200 virtual bool fiqDisable(ThreadContext *tc) = 0; 201 virtual ExceptionClass ec(ThreadContext *tc) const = 0; 202 virtual uint32_t iss() const = 0; 203 virtual bool isStage2() const { return false; } 204 virtual FSR getFsr(ThreadContext *tc) { return 0; } 205 virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg);
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120}; 121 122template<typename T> 123class ArmFaultVals : public ArmFault 124{ 125 protected: 126 static FaultVals vals; 127 128 public:
| 206}; 207 208template<typename T> 209class ArmFaultVals : public ArmFault 210{ 211 protected: 212 static FaultVals vals; 213 214 public:
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| 215 ArmFaultVals<T>(ExtMachInst _machInst = 0, uint32_t _iss = 0) : 216 ArmFault(_machInst, _iss) {}
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129 FaultName name() const { return vals.name; }
| 217 FaultName name() const { return vals.name; }
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130 FaultStat & countStat() {return vals.count;} 131 FaultOffset offset() { return vals.offset; }
| 218 FaultStat & countStat() { return vals.count; } 219 FaultOffset offset(ThreadContext *tc); 220 221 FaultOffset 222 offset64() 223 { 224 if (toEL == fromEL) { 225 if (opModeIsT(fromMode)) 226 return vals.currELTOffset; 227 return vals.currELHOffset; 228 } else { 229 if (from64) 230 return vals.lowerEL64Offset; 231 return vals.lowerEL32Offset; 232 } 233 } 234
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132 OperatingMode nextMode() { return vals.nextMode; }
| 235 OperatingMode nextMode() { return vals.nextMode; }
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133 uint8_t armPcOffset() { return vals.armPcOffset; } 134 uint8_t thumbPcOffset() { return vals.thumbPcOffset; } 135 bool abortDisable() { return vals.abortDisable; } 136 bool fiqDisable() { return vals.fiqDisable; }
| 236 virtual bool routeToMonitor(ThreadContext *tc) const { return false; } 237 uint8_t armPcOffset(bool isHyp) { return isHyp ? vals.armPcElrOffset 238 : vals.armPcOffset; } 239 uint8_t thumbPcOffset(bool isHyp) { return isHyp ? vals.thumbPcElrOffset 240 : vals.thumbPcOffset; } 241 uint8_t armPcElrOffset() { return vals.armPcElrOffset; } 242 uint8_t thumbPcElrOffset() { return vals.thumbPcElrOffset; } 243 virtual bool abortDisable(ThreadContext* tc) { return vals.abortDisable; } 244 virtual bool fiqDisable(ThreadContext* tc) { return vals.fiqDisable; } 245 virtual ExceptionClass ec(ThreadContext *tc) const { return vals.ec; } 246 virtual uint32_t iss() const { return issRaw; }
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137}; 138 139class Reset : public ArmFaultVals<Reset> 140{ 141 public: 142 void invoke(ThreadContext *tc, 143 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 144}; 145 146class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction> 147{ 148 protected:
| 247}; 248 249class Reset : public ArmFaultVals<Reset> 250{ 251 public: 252 void invoke(ThreadContext *tc, 253 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 254}; 255 256class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction> 257{ 258 protected:
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149 ExtMachInst machInst;
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150 bool unknown; 151 const char *mnemonic; 152 bool disabled;
| 259 bool unknown; 260 const char *mnemonic; 261 bool disabled;
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| 262 ExceptionClass overrideEc;
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153 154 public: 155 UndefinedInstruction(ExtMachInst _machInst, 156 bool _unknown, 157 const char *_mnemonic = NULL, 158 bool _disabled = false) :
| 263 264 public: 265 UndefinedInstruction(ExtMachInst _machInst, 266 bool _unknown, 267 const char *_mnemonic = NULL, 268 bool _disabled = false) :
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159 machInst(_machInst), unknown(_unknown), 160 mnemonic(_mnemonic), disabled(_disabled) 161 { 162 } 163 UndefinedInstruction() : 164 machInst(0), unknown(false), mnemonic("undefined"), disabled(false)
| 269 ArmFaultVals<UndefinedInstruction>(_machInst), 270 unknown(_unknown), mnemonic(_mnemonic), disabled(_disabled), 271 overrideEc(EC_INVALID)
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165 {}
| 272 {}
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| 273 UndefinedInstruction(ExtMachInst _machInst, uint32_t _iss, ExceptionClass _overrideEc) : 274 ArmFaultVals<UndefinedInstruction>(_machInst, _iss), 275 overrideEc(_overrideEc) 276 {}
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166 167 void invoke(ThreadContext *tc, 168 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
| 277 278 void invoke(ThreadContext *tc, 279 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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| 280 bool routeToHyp(ThreadContext *tc) const; 281 ExceptionClass ec(ThreadContext *tc) const; 282 uint32_t iss() const;
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169}; 170 171class SupervisorCall : public ArmFaultVals<SupervisorCall> 172{ 173 protected:
| 283}; 284 285class SupervisorCall : public ArmFaultVals<SupervisorCall> 286{ 287 protected:
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174 ExtMachInst machInst;
| 288 ExceptionClass overrideEc; 289 public: 290 SupervisorCall(ExtMachInst _machInst, uint32_t _iss, 291 ExceptionClass _overrideEc = EC_INVALID) : 292 ArmFaultVals<SupervisorCall>(_machInst, _iss), 293 overrideEc(_overrideEc) 294 {}
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175
| 295
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| 296 void invoke(ThreadContext *tc, 297 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 298 bool routeToHyp(ThreadContext *tc) const; 299 ExceptionClass ec(ThreadContext *tc) const; 300 uint32_t iss() const; 301}; 302 303class SecureMonitorCall : public ArmFaultVals<SecureMonitorCall> 304{
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176 public:
| 305 public:
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177 SupervisorCall(ExtMachInst _machInst) : machInst(_machInst)
| 306 SecureMonitorCall(ExtMachInst _machInst) : 307 ArmFaultVals<SecureMonitorCall>(_machInst)
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178 {}
| 308 {}
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179 SupervisorCall() : machInst(0) 180 {}
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181 182 void invoke(ThreadContext *tc, 183 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
| 309 310 void invoke(ThreadContext *tc, 311 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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| 312 ExceptionClass ec(ThreadContext *tc) const; 313 uint32_t iss() const;
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184}; 185
| 314}; 315
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| 316class SupervisorTrap : public ArmFaultVals<SupervisorTrap> 317{ 318 protected: 319 ExtMachInst machInst; 320 ExceptionClass overrideEc; 321 322 public: 323 SupervisorTrap(ExtMachInst _machInst, uint32_t _iss, 324 ExceptionClass _overrideEc = EC_INVALID) : 325 ArmFaultVals<SupervisorTrap>(_machInst, _iss), 326 overrideEc(_overrideEc) 327 {} 328 329 ExceptionClass ec(ThreadContext *tc) const; 330}; 331 332class SecureMonitorTrap : public ArmFaultVals<SecureMonitorTrap> 333{ 334 protected: 335 ExtMachInst machInst; 336 ExceptionClass overrideEc; 337 338 public: 339 SecureMonitorTrap(ExtMachInst _machInst, uint32_t _iss, 340 ExceptionClass _overrideEc = EC_INVALID) : 341 ArmFaultVals<SecureMonitorTrap>(_machInst, _iss), 342 overrideEc(_overrideEc) 343 {} 344 345 ExceptionClass ec(ThreadContext *tc) const; 346}; 347 348class HypervisorCall : public ArmFaultVals<HypervisorCall> 349{ 350 public: 351 HypervisorCall(ExtMachInst _machInst, uint32_t _imm); 352}; 353 354class HypervisorTrap : public ArmFaultVals<HypervisorTrap> 355{ 356 protected: 357 ExtMachInst machInst; 358 ExceptionClass overrideEc; 359 360 public: 361 HypervisorTrap(ExtMachInst _machInst, uint32_t _iss, 362 ExceptionClass _overrideEc = EC_INVALID) : 363 ArmFaultVals<HypervisorTrap>(_machInst, _iss), 364 overrideEc(_overrideEc) 365 {} 366 367 ExceptionClass ec(ThreadContext *tc) const; 368}; 369
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186template <class T> 187class AbortFault : public ArmFaultVals<T> 188{ 189 protected:
| 370template <class T> 371class AbortFault : public ArmFaultVals<T> 372{ 373 protected:
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| 374 /** 375 * The virtual address the fault occured at. If 2 stages of 376 * translation are being used then this is the intermediate 377 * physical address that is the starting point for the second 378 * stage of translation. 379 */
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190 Addr faultAddr;
| 380 Addr faultAddr;
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| 381 /** 382 * Original virtual address. If the fault was generated on the 383 * second stage of translation then this variable stores the 384 * virtual address used in the original stage 1 translation. 385 */ 386 Addr OVAddr;
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191 bool write;
| 387 bool write;
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192 uint8_t domain; 193 uint8_t status;
| 388 TlbEntry::DomainType domain; 389 uint8_t source; 390 uint8_t srcEncoded; 391 bool stage2; 392 bool s1ptw; 393 ArmFault::TranMethod tranMethod;
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194 195 public:
| 394 395 public:
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196 AbortFault(Addr _faultAddr, bool _write, 197 uint8_t _domain, uint8_t _status) : 198 faultAddr(_faultAddr), write(_write), 199 domain(_domain), status(_status)
| 396 AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain, uint8_t _source, 397 bool _stage2, ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 398 faultAddr(_faultAddr), write(_write), domain(_domain), source(_source), 399 stage2(_stage2), s1ptw(false), tranMethod(_tranMethod)
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200 {} 201 202 void invoke(ThreadContext *tc, 203 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
| 400 {} 401 402 void invoke(ThreadContext *tc, 403 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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| 404 405 FSR getFsr(ThreadContext *tc); 406 bool abortDisable(ThreadContext *tc); 407 uint32_t iss() const; 408 bool isStage2() const { return stage2; } 409 void annotate(ArmFault::AnnotationIDs id, uint64_t val); 410 bool isMMUFault() const;
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204}; 205 206class PrefetchAbort : public AbortFault<PrefetchAbort> 207{ 208 public:
| 411}; 412 413class PrefetchAbort : public AbortFault<PrefetchAbort> 414{ 415 public:
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209 static const MiscRegIndex FsrIndex = MISCREG_IFSR; 210 static const MiscRegIndex FarIndex = MISCREG_IFAR;
| 416 static const MiscRegIndex FsrIndex = MISCREG_IFSR; 417 static const MiscRegIndex FarIndex = MISCREG_IFAR; 418 static const MiscRegIndex HFarIndex = MISCREG_HIFAR;
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211
| 419
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212 PrefetchAbort(Addr _addr, uint8_t _status) : 213 AbortFault<PrefetchAbort>(_addr, false, 0, _status)
| 420 PrefetchAbort(Addr _addr, uint8_t _source, bool _stage2 = false, 421 ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 422 AbortFault<PrefetchAbort>(_addr, false, TlbEntry::DomainType::NoAccess, 423 _source, _stage2, _tranMethod)
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214 {}
| 424 {}
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| 425 426 ExceptionClass ec(ThreadContext *tc) const; 427 // @todo: external aborts should be routed if SCR.EA == 1 428 bool routeToMonitor(ThreadContext *tc) const; 429 bool routeToHyp(ThreadContext *tc) const;
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215}; 216 217class DataAbort : public AbortFault<DataAbort> 218{ 219 public:
| 430}; 431 432class DataAbort : public AbortFault<DataAbort> 433{ 434 public:
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220 static const MiscRegIndex FsrIndex = MISCREG_DFSR; 221 static const MiscRegIndex FarIndex = MISCREG_DFAR;
| 435 static const MiscRegIndex FsrIndex = MISCREG_DFSR; 436 static const MiscRegIndex FarIndex = MISCREG_DFAR; 437 static const MiscRegIndex HFarIndex = MISCREG_HDFAR; 438 bool isv; 439 uint8_t sas; 440 uint8_t sse; 441 uint8_t srt;
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222
| 442
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223 DataAbort(Addr _addr, uint8_t _domain, bool _write, uint8_t _status) : 224 AbortFault<DataAbort>(_addr, _write, _domain, _status)
| 443 // AArch64 only 444 bool sf; 445 bool ar; 446 447 DataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source, 448 bool _stage2 = false, ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 449 AbortFault<DataAbort>(_addr, _write, _domain, _source, _stage2, 450 _tranMethod), 451 isv(false), sas (0), sse(0), srt(0), sf(false), ar(false)
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225 {}
| 452 {}
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| 453 454 ExceptionClass ec(ThreadContext *tc) const; 455 // @todo: external aborts should be routed if SCR.EA == 1 456 bool routeToMonitor(ThreadContext *tc) const; 457 bool routeToHyp(ThreadContext *tc) const; 458 uint32_t iss() const; 459 void annotate(AnnotationIDs id, uint64_t val);
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226}; 227
| 460}; 461
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228class Interrupt : public ArmFaultVals<Interrupt> {}; 229class FastInterrupt : public ArmFaultVals<FastInterrupt> {};
| 462class VirtualDataAbort : public AbortFault<VirtualDataAbort> 463{ 464 public: 465 static const MiscRegIndex FsrIndex = MISCREG_DFSR; 466 static const MiscRegIndex FarIndex = MISCREG_DFAR; 467 static const MiscRegIndex HFarIndex = MISCREG_HDFAR;
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230
| 468
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| 469 VirtualDataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, 470 uint8_t _source) : 471 AbortFault<VirtualDataAbort>(_addr, _write, _domain, _source, false) 472 {} 473 474 void invoke(ThreadContext *tc, StaticInstPtr inst); 475}; 476 477class Interrupt : public ArmFaultVals<Interrupt> 478{ 479 public: 480 bool routeToMonitor(ThreadContext *tc) const; 481 bool routeToHyp(ThreadContext *tc) const; 482 bool abortDisable(ThreadContext *tc); 483}; 484 485class VirtualInterrupt : public ArmFaultVals<VirtualInterrupt> 486{ 487 public: 488 VirtualInterrupt(); 489}; 490 491class FastInterrupt : public ArmFaultVals<FastInterrupt> 492{ 493 public: 494 bool routeToMonitor(ThreadContext *tc) const; 495 bool routeToHyp(ThreadContext *tc) const; 496 bool abortDisable(ThreadContext *tc); 497 bool fiqDisable(ThreadContext *tc); 498}; 499 500class VirtualFastInterrupt : public ArmFaultVals<VirtualFastInterrupt> 501{ 502 public: 503 VirtualFastInterrupt(); 504}; 505 506/// PC alignment fault (AArch64 only) 507class PCAlignmentFault : public ArmFaultVals<PCAlignmentFault> 508{ 509 protected: 510 /// The unaligned value of the PC 511 Addr faultPC; 512 public: 513 PCAlignmentFault(Addr _faultPC) : faultPC(_faultPC) 514 {} 515 void invoke(ThreadContext *tc, 516 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 517}; 518 519/// Stack pointer alignment fault (AArch64 only) 520class SPAlignmentFault : public ArmFaultVals<SPAlignmentFault> 521{ 522 public: 523 SPAlignmentFault(); 524}; 525 526/// System error (AArch64 only) 527class SystemError : public ArmFaultVals<SystemError> 528{ 529 public: 530 SystemError(); 531 void invoke(ThreadContext *tc, 532 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 533 bool routeToMonitor(ThreadContext *tc) const; 534 bool routeToHyp(ThreadContext *tc) const; 535}; 536
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231// A fault that flushes the pipe, excluding the faulting instructions 232class FlushPipe : public ArmFaultVals<FlushPipe> 233{ 234 public: 235 FlushPipe() {} 236 void invoke(ThreadContext *tc, 237 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 238}; 239 240// A fault that flushes the pipe, excluding the faulting instructions 241class ArmSev : public ArmFaultVals<ArmSev> 242{ 243 public: 244 ArmSev () {} 245 void invoke(ThreadContext *tc, 246 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 247}; 248
| 537// A fault that flushes the pipe, excluding the faulting instructions 538class FlushPipe : public ArmFaultVals<FlushPipe> 539{ 540 public: 541 FlushPipe() {} 542 void invoke(ThreadContext *tc, 543 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 544}; 545 546// A fault that flushes the pipe, excluding the faulting instructions 547class ArmSev : public ArmFaultVals<ArmSev> 548{ 549 public: 550 ArmSev () {} 551 void invoke(ThreadContext *tc, 552 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 553}; 554
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| 555/// Illegal Instruction Set State fault (AArch64 only) 556class IllegalInstSetStateFault : public ArmFaultVals<IllegalInstSetStateFault> 557{ 558 public: 559 IllegalInstSetStateFault(); 560}; 561
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249} // namespace ArmISA 250 251#endif // __ARM_FAULTS_HH__
| 562} // namespace ArmISA 563 564#endif // __ARM_FAULTS_HH__
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