1/*
2 * Copyright (c) 2010, 2012-2013, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 * Gabe Black
43 * Giacomo Gabrielli
44 * Thomas Grocutt
45 */
46
47#ifndef __ARM_FAULTS_HH__
48#define __ARM_FAULTS_HH__
49
50#include "arch/arm/miscregs.hh"
51#include "arch/arm/pagetable.hh"
52#include "arch/arm/types.hh"
53#include "base/logging.hh"
54#include "sim/faults.hh"
55#include "sim/full_system.hh"
56
57// The design of the "name" and "vect" functions is in sim/faults.hh
58
59namespace ArmISA
60{
61typedef Addr FaultOffset;
62
63class ArmStaticInst;
64
65class ArmFault : public FaultBase
66{
67 protected:
68 ExtMachInst machInst;
69 uint32_t issRaw;
70
71 // Helper variables for ARMv8 exception handling
72 bool from64; // True if the exception is generated from the AArch64 state
73 bool to64; // True if the exception is taken in AArch64 state
74 ExceptionLevel fromEL; // Source exception level
75 ExceptionLevel toEL; // Target exception level
76 OperatingMode fromMode; // Source operating mode (aarch32)
77 OperatingMode toMode; // Next operating mode (aarch32)
78
79 // This variable is true if the above fault specific informations
80 // have been updated. This is to prevent that a client is using their
81 // un-updated default constructed value.
82 bool faultUpdated;
83
84 bool hypRouted; // True if the fault has been routed to Hypervisor
85
86 virtual Addr getVector(ThreadContext *tc);
87 Addr getVector64(ThreadContext *tc);
88
89 public:
90 /// Generic fault source enums used to index into
91 /// {short/long/aarch64}DescFaultSources[] to get the actual encodings based
92 /// on the current register width state and the translation table format in
93 /// use
94 enum FaultSource
95 {
96 AlignmentFault = 0,
97 InstructionCacheMaintenance, // Short-desc. format only
98 SynchExtAbtOnTranslTableWalkLL,
99 SynchPtyErrOnTranslTableWalkLL = SynchExtAbtOnTranslTableWalkLL + 4,
100 TranslationLL = SynchPtyErrOnTranslTableWalkLL + 4,
101 AccessFlagLL = TranslationLL + 4,
102 DomainLL = AccessFlagLL + 4,
103 PermissionLL = DomainLL + 4,
104 DebugEvent = PermissionLL + 4,
105 SynchronousExternalAbort,
106 TLBConflictAbort, // Requires LPAE
107 SynchPtyErrOnMemoryAccess,
108 AsynchronousExternalAbort,
109 AsynchPtyErrOnMemoryAccess,
110 AddressSizeLL, // AArch64 only
111
112 // Not real faults. These are faults to allow the translation function
113 // to inform the memory access function not to proceed for a prefetch
114 // that misses in the TLB or that targets an uncacheable address
115 PrefetchTLBMiss = AddressSizeLL + 4,
116 PrefetchUncacheable,
117
118 NumFaultSources,
119 FaultSourceInvalid = 0xff
120 };
121
122 /// Encodings of the fault sources when the short-desc. translation table
123 /// format is in use (ARM ARM Issue C B3.13.3)
124 static uint8_t shortDescFaultSources[NumFaultSources];
125 /// Encodings of the fault sources when the long-desc. translation table
126 /// format is in use (ARM ARM Issue C B3.13.3)
127 static uint8_t longDescFaultSources[NumFaultSources];
128 /// Encodings of the fault sources in AArch64 state
129 static uint8_t aarch64FaultSources[NumFaultSources];
130
131 enum AnnotationIDs
132 {
133 S1PTW, // DataAbort, PrefetchAbort: Stage 1 Page Table Walk,
134 OVA, // DataAbort, PrefetchAbort: stage 1 Virtual Address for stage 2 faults
135 SAS, // DataAbort: Syndrome Access Size
136 SSE, // DataAbort: Syndrome Sign Extend
137 SRT, // DataAbort: Syndrome Register Transfer
138
139 // AArch64 only
140 SF, // DataAbort: width of the accessed register is SixtyFour
141 AR // DataAbort: Acquire/Release semantics
142 };
143
144 enum TranMethod
145 {
146 LpaeTran,
147 VmsaTran,
148 UnknownTran
149 };
150
151 struct FaultVals
152 {
153 const FaultName name;
154
155 const FaultOffset offset;
156
157 // Offsets used for exceptions taken in AArch64 state
158 const uint16_t currELTOffset;
159 const uint16_t currELHOffset;
160 const uint16_t lowerEL64Offset;
161 const uint16_t lowerEL32Offset;
162
163 const OperatingMode nextMode;
164
165 const uint8_t armPcOffset;
166 const uint8_t thumbPcOffset;
167 // The following two values are used in place of armPcOffset and
168 // thumbPcOffset when the exception return address is saved into ELR
169 // registers (exceptions taken in HYP mode or in AArch64 state)
170 const uint8_t armPcElrOffset;
171 const uint8_t thumbPcElrOffset;
172
173 const bool hypTrappable;
174 const bool abortDisable;
175 const bool fiqDisable;
176
177 // Exception class used to appropriately set the syndrome register
178 // (exceptions taken in HYP mode or in AArch64 state)
179 const ExceptionClass ec;
180
181 FaultStat count;
182 FaultVals(const FaultName& name_, const FaultOffset& offset_,
183 const uint16_t& currELTOffset_, const uint16_t& currELHOffset_,
184 const uint16_t& lowerEL64Offset_,
185 const uint16_t& lowerEL32Offset_,
186 const OperatingMode& nextMode_, const uint8_t& armPcOffset_,
187 const uint8_t& thumbPcOffset_, const uint8_t& armPcElrOffset_,
188 const uint8_t& thumbPcElrOffset_, const bool& hypTrappable_,
189 const bool& abortDisable_, const bool& fiqDisable_,
190 const ExceptionClass& ec_)
191 : name(name_), offset(offset_), currELTOffset(currELTOffset_),
192 currELHOffset(currELHOffset_), lowerEL64Offset(lowerEL64Offset_),
193 lowerEL32Offset(lowerEL32Offset_), nextMode(nextMode_),
194 armPcOffset(armPcOffset_), thumbPcOffset(thumbPcOffset_),
195 armPcElrOffset(armPcElrOffset_), thumbPcElrOffset(thumbPcElrOffset_),
196 hypTrappable(hypTrappable_), abortDisable(abortDisable_),
197 fiqDisable(fiqDisable_), ec(ec_) {}
198 };
199
200 ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
201 machInst(_machInst), issRaw(_iss), from64(false), to64(false),
202 fromEL(EL0), toEL(EL0), fromMode(MODE_UNDEFINED),
203 faultUpdated(false), hypRouted(false) {}
204
205 // Returns the actual syndrome register to use based on the target
206 // exception level
207 MiscRegIndex getSyndromeReg64() const;
208 // Returns the actual fault address register to use based on the target
209 // exception level
210 MiscRegIndex getFaultAddrReg64() const;
211
212 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
213 StaticInst::nullStaticInstPtr) override;
214 void invoke64(ThreadContext *tc, const StaticInstPtr &inst =
215 StaticInst::nullStaticInstPtr);
216 void update(ThreadContext *tc);
217
218 ArmStaticInst *instrAnnotate(const StaticInstPtr &inst);
219 virtual void annotate(AnnotationIDs id, uint64_t val) {}
220 virtual FaultStat& countStat() = 0;
221 virtual FaultOffset offset(ThreadContext *tc) = 0;
222 virtual FaultOffset offset64(ThreadContext *tc) = 0;
223 virtual OperatingMode nextMode() = 0;
224 virtual bool routeToMonitor(ThreadContext *tc) const = 0;
225 virtual bool routeToHyp(ThreadContext *tc) const { return false; }
226 virtual uint8_t armPcOffset(bool isHyp) = 0;
227 virtual uint8_t thumbPcOffset(bool isHyp) = 0;
228 virtual uint8_t armPcElrOffset() = 0;
229 virtual uint8_t thumbPcElrOffset() = 0;
230 virtual bool abortDisable(ThreadContext *tc) = 0;
231 virtual bool fiqDisable(ThreadContext *tc) = 0;
232 virtual ExceptionClass ec(ThreadContext *tc) const = 0;
233 virtual uint32_t iss() const = 0;
234 virtual bool isStage2() const { return false; }
235 virtual FSR getFsr(ThreadContext *tc) const { return 0; }
236 virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg);
237};
238
239template<typename T>
240class ArmFaultVals : public ArmFault
241{
242 protected:
243 static FaultVals vals;
244
245 public:
246 ArmFaultVals<T>(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
247 ArmFault(_machInst, _iss) {}
248 FaultName name() const override { return vals.name; }
249 FaultStat & countStat() override { return vals.count; }
250 FaultOffset offset(ThreadContext *tc) override;
251
252 FaultOffset offset64(ThreadContext *tc) override;
253
254 OperatingMode nextMode() override { return vals.nextMode; }
255 virtual bool routeToMonitor(ThreadContext *tc) const override {
256 return false;
257 }
258 uint8_t armPcOffset(bool isHyp) override {
259 return isHyp ? vals.armPcElrOffset
260 : vals.armPcOffset;
261 }
262 uint8_t thumbPcOffset(bool isHyp) override {
263 return isHyp ? vals.thumbPcElrOffset
264 : vals.thumbPcOffset;
265 }
266 uint8_t armPcElrOffset() override { return vals.armPcElrOffset; }
267 uint8_t thumbPcElrOffset() override { return vals.thumbPcElrOffset; }
268 bool abortDisable(ThreadContext* tc) override { return vals.abortDisable; }
269 bool fiqDisable(ThreadContext* tc) override { return vals.fiqDisable; }
270 ExceptionClass ec(ThreadContext *tc) const override { return vals.ec; }
271 uint32_t iss() const override { return issRaw; }
272};
273
274class Reset : public ArmFaultVals<Reset>
275{
276 protected:
277 Addr getVector(ThreadContext *tc) override;
278
279 public:
280 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
281 StaticInst::nullStaticInstPtr) override;
282};
283
284class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
285{
286 protected:
287 bool unknown;
288 bool disabled;
289 ExceptionClass overrideEc;
290 const char *mnemonic;
291
292 public:
293 UndefinedInstruction(ExtMachInst _machInst,
294 bool _unknown,
295 const char *_mnemonic = NULL,
296 bool _disabled = false) :
297 ArmFaultVals<UndefinedInstruction>(_machInst),
298 unknown(_unknown), disabled(_disabled),
299 overrideEc(EC_INVALID), mnemonic(_mnemonic)
300 {}
301 UndefinedInstruction(ExtMachInst _machInst, uint32_t _iss,
302 ExceptionClass _overrideEc, const char *_mnemonic = NULL) :
303 ArmFaultVals<UndefinedInstruction>(_machInst, _iss),
304 unknown(false), disabled(true), overrideEc(_overrideEc),
305 mnemonic(_mnemonic)
306 {}
307
308 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
309 StaticInst::nullStaticInstPtr) override;
310 bool routeToHyp(ThreadContext *tc) const override;
311 ExceptionClass ec(ThreadContext *tc) const override;
312 uint32_t iss() const override;
313};
314
315class SupervisorCall : public ArmFaultVals<SupervisorCall>
316{
317 protected:
318 ExceptionClass overrideEc;
319 public:
320 SupervisorCall(ExtMachInst _machInst, uint32_t _iss,
321 ExceptionClass _overrideEc = EC_INVALID) :
322 ArmFaultVals<SupervisorCall>(_machInst, _iss),
323 overrideEc(_overrideEc)
324 {}
325
326 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
327 StaticInst::nullStaticInstPtr) override;
328 bool routeToHyp(ThreadContext *tc) const override;
329 ExceptionClass ec(ThreadContext *tc) const override;
330 uint32_t iss() const override;
331};
332
333class SecureMonitorCall : public ArmFaultVals<SecureMonitorCall>
334{
335 public:
336 SecureMonitorCall(ExtMachInst _machInst) :
337 ArmFaultVals<SecureMonitorCall>(_machInst)
338 {}
339
340 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
341 StaticInst::nullStaticInstPtr) override;
342 ExceptionClass ec(ThreadContext *tc) const override;
343 uint32_t iss() const override;
344};
345
346class SupervisorTrap : public ArmFaultVals<SupervisorTrap>
347{
348 protected:
349 ExtMachInst machInst;
350 ExceptionClass overrideEc;
351
352 public:
353 SupervisorTrap(ExtMachInst _machInst, uint32_t _iss,
354 ExceptionClass _overrideEc = EC_INVALID) :
355 ArmFaultVals<SupervisorTrap>(_machInst, _iss),
356 overrideEc(_overrideEc)
357 {}
358
359 bool routeToHyp(ThreadContext *tc) const override;
360 uint32_t iss() const override;
361 ExceptionClass ec(ThreadContext *tc) const override;
362};
363
364class SecureMonitorTrap : public ArmFaultVals<SecureMonitorTrap>
365{
366 protected:
367 ExtMachInst machInst;
368 ExceptionClass overrideEc;
369
370 public:
371 SecureMonitorTrap(ExtMachInst _machInst, uint32_t _iss,
372 ExceptionClass _overrideEc = EC_INVALID) :
373 ArmFaultVals<SecureMonitorTrap>(_machInst, _iss),
374 overrideEc(_overrideEc)
375 {}
376
377 ExceptionClass ec(ThreadContext *tc) const override;
378};
379
380class HypervisorCall : public ArmFaultVals<HypervisorCall>
381{
382 public:
383 HypervisorCall(ExtMachInst _machInst, uint32_t _imm);
384
385 ExceptionClass ec(ThreadContext *tc) const override;
386};
387
388class HypervisorTrap : public ArmFaultVals<HypervisorTrap>
389{
390 protected:
391 ExtMachInst machInst;
392 ExceptionClass overrideEc;
393
394 public:
395 HypervisorTrap(ExtMachInst _machInst, uint32_t _iss,
396 ExceptionClass _overrideEc = EC_INVALID) :
397 ArmFaultVals<HypervisorTrap>(_machInst, _iss),
398 overrideEc(_overrideEc)
399 {}
400
401 ExceptionClass ec(ThreadContext *tc) const override;
402};
403
404template <class T>
405class AbortFault : public ArmFaultVals<T>
406{
407 protected:
408 /**
409 * The virtual address the fault occured at. If 2 stages of
410 * translation are being used then this is the intermediate
411 * physical address that is the starting point for the second
412 * stage of translation.
413 */
414 Addr faultAddr;
415 /**
416 * Original virtual address. If the fault was generated on the
417 * second stage of translation then this variable stores the
418 * virtual address used in the original stage 1 translation.
419 */
420 Addr OVAddr;
421 bool write;
422 TlbEntry::DomainType domain;
423 uint8_t source;
424 uint8_t srcEncoded;
425 bool stage2;
426 bool s1ptw;
427 ArmFault::TranMethod tranMethod;
428
429 public:
430 AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain,
431 uint8_t _source, bool _stage2,
432 ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) :
433 faultAddr(_faultAddr), OVAddr(0), write(_write),
434 domain(_domain), source(_source), srcEncoded(0),
435 stage2(_stage2), s1ptw(false), tranMethod(_tranMethod)
436 {}
437
438 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
439 StaticInst::nullStaticInstPtr) override;
440
441 FSR getFsr(ThreadContext *tc) const override;
442 uint8_t getFaultStatusCode(ThreadContext *tc) const;
443 bool abortDisable(ThreadContext *tc) override;
444 uint32_t iss() const override;
445 bool isStage2() const override { return stage2; }
446 void annotate(ArmFault::AnnotationIDs id, uint64_t val) override;
447 void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) override;
448 bool isMMUFault() const;
449};
450
451class PrefetchAbort : public AbortFault<PrefetchAbort>
452{
453 public:
454 static const MiscRegIndex FsrIndex = MISCREG_IFSR;
455 static const MiscRegIndex FarIndex = MISCREG_IFAR;
456 static const MiscRegIndex HFarIndex = MISCREG_HIFAR;
457
458 PrefetchAbort(Addr _addr, uint8_t _source, bool _stage2 = false,
459 ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) :
460 AbortFault<PrefetchAbort>(_addr, false, TlbEntry::DomainType::NoAccess,
461 _source, _stage2, _tranMethod)
462 {}
463
464 ExceptionClass ec(ThreadContext *tc) const override;
465 // @todo: external aborts should be routed if SCR.EA == 1
466 bool routeToMonitor(ThreadContext *tc) const override;
467 bool routeToHyp(ThreadContext *tc) const override;
468};
469
470class DataAbort : public AbortFault<DataAbort>
471{
472 public:
473 static const MiscRegIndex FsrIndex = MISCREG_DFSR;
474 static const MiscRegIndex FarIndex = MISCREG_DFAR;
475 static const MiscRegIndex HFarIndex = MISCREG_HDFAR;
476 bool isv;
477 uint8_t sas;
478 uint8_t sse;
479 uint8_t srt;
480
481 // AArch64 only
482 bool sf;
483 bool ar;
484
485 DataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source,
486 bool _stage2 = false, ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) :
487 AbortFault<DataAbort>(_addr, _write, _domain, _source, _stage2,
488 _tranMethod),
489 isv(false), sas (0), sse(0), srt(0), sf(false), ar(false)
490 {}
491
492 ExceptionClass ec(ThreadContext *tc) const override;
493 // @todo: external aborts should be routed if SCR.EA == 1
494 bool routeToMonitor(ThreadContext *tc) const override;
495 bool routeToHyp(ThreadContext *tc) const override;
496 uint32_t iss() const override;
497 void annotate(AnnotationIDs id, uint64_t val) override;
498};
499
500class VirtualDataAbort : public AbortFault<VirtualDataAbort>
501{
502 public:
503 static const MiscRegIndex FsrIndex = MISCREG_DFSR;
504 static const MiscRegIndex FarIndex = MISCREG_DFAR;
505 static const MiscRegIndex HFarIndex = MISCREG_HDFAR;
506
507 VirtualDataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write,
508 uint8_t _source) :
509 AbortFault<VirtualDataAbort>(_addr, _write, _domain, _source, false)
510 {}
511
512 void invoke(ThreadContext *tc, const StaticInstPtr &inst) override;
513};
514
515class Interrupt : public ArmFaultVals<Interrupt>
516{
517 public:
518 bool routeToMonitor(ThreadContext *tc) const override;
519 bool routeToHyp(ThreadContext *tc) const override;
520 bool abortDisable(ThreadContext *tc) override;
521};
522
523class VirtualInterrupt : public ArmFaultVals<VirtualInterrupt>
524{
525 public:
526 VirtualInterrupt();
527};
528
529class FastInterrupt : public ArmFaultVals<FastInterrupt>
530{
531 public:
532 bool routeToMonitor(ThreadContext *tc) const override;
533 bool routeToHyp(ThreadContext *tc) const override;
534 bool abortDisable(ThreadContext *tc) override;
535 bool fiqDisable(ThreadContext *tc) override;
536};
537
538class VirtualFastInterrupt : public ArmFaultVals<VirtualFastInterrupt>
539{
540 public:
541 VirtualFastInterrupt();
542};
543
544/// PC alignment fault (AArch64 only)
545class PCAlignmentFault : public ArmFaultVals<PCAlignmentFault>
546{
547 protected:
548 /// The unaligned value of the PC
549 Addr faultPC;
550 public:
551 PCAlignmentFault(Addr _faultPC) : faultPC(_faultPC)
552 {}
553 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
554 StaticInst::nullStaticInstPtr) override;
555 bool routeToHyp(ThreadContext *tc) const override;
556};
557
558/// Stack pointer alignment fault (AArch64 only)
559class SPAlignmentFault : public ArmFaultVals<SPAlignmentFault>
560{
561 public:
562 SPAlignmentFault();
563};
564
565/// System error (AArch64 only)
566class SystemError : public ArmFaultVals<SystemError>
567{
568 public:
569 SystemError();
570 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
571 StaticInst::nullStaticInstPtr) override;
572 bool routeToMonitor(ThreadContext *tc) const override;
573 bool routeToHyp(ThreadContext *tc) const override;
574};
575
576/// System error (AArch64 only)
577class SoftwareBreakpoint : public ArmFaultVals<SoftwareBreakpoint>
578{
579 public:
580 SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss);
581
582 bool routeToHyp(ThreadContext *tc) const override;
583 ExceptionClass ec(ThreadContext *tc) const override;
584};
585
586// A fault that flushes the pipe, excluding the faulting instructions
587class ArmSev : public ArmFaultVals<ArmSev>
588{
589 public:
590 ArmSev () {}
591 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
592 StaticInst::nullStaticInstPtr) override;
593};
594
595/// Illegal Instruction Set State fault (AArch64 only)
596class IllegalInstSetStateFault : public ArmFaultVals<IllegalInstSetStateFault>
597{
598 public:
599 IllegalInstSetStateFault();
600};
601
602/*
603 * Explicitly declare template static member variables to avoid warnings
604 * in some clang versions
605 */
606template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals;
607template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals;
608template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals;
609template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals;
610template<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals;
611template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals;
612template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals;
613template<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals;
614template<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals;
615template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals;
616template<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals;
617template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals;
618template<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals;
619template<> ArmFault::FaultVals ArmFaultVals<IllegalInstSetStateFault>::vals;
620template<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals;
621template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals;
622template<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals;
623template<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals;
624template<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals;
625template<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals;
626template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals;
627
628
629} // namespace ArmISA
630
631#endif // __ARM_FAULTS_HH__