1/*
2 * Copyright (c) 2010, 2012-2013, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 * Gabe Black
43 * Giacomo Gabrielli
44 * Thomas Grocutt
45 */
46
47#ifndef __ARM_FAULTS_HH__
48#define __ARM_FAULTS_HH__
49
50#include "arch/arm/miscregs.hh"
51#include "arch/arm/pagetable.hh"
52#include "arch/arm/types.hh"
53#include "base/logging.hh"
54#include "sim/faults.hh"
55#include "sim/full_system.hh"
56
57// The design of the "name" and "vect" functions is in sim/faults.hh
58
59namespace ArmISA
60{
61typedef Addr FaultOffset;
62
63class ArmFault : public FaultBase
64{
65 protected:
66 ExtMachInst machInst;
67 uint32_t issRaw;
68
69 // Helper variables for ARMv8 exception handling
70 bool from64; // True if the exception is generated from the AArch64 state
71 bool to64; // True if the exception is taken in AArch64 state
72 ExceptionLevel fromEL; // Source exception level
73 ExceptionLevel toEL; // Target exception level
74 OperatingMode fromMode; // Source operating mode
75
76 bool hypRouted; // True if the fault has been routed to Hypervisor
77
78 Addr getVector(ThreadContext *tc);
79 Addr getVector64(ThreadContext *tc);
80
81 public:
82 /// Generic fault source enums used to index into
83 /// {short/long/aarch64}DescFaultSources[] to get the actual encodings based
84 /// on the current register width state and the translation table format in
85 /// use
86 enum FaultSource
87 {
88 AlignmentFault = 0,
89 InstructionCacheMaintenance, // Short-desc. format only
90 SynchExtAbtOnTranslTableWalkLL,
91 SynchPtyErrOnTranslTableWalkLL = SynchExtAbtOnTranslTableWalkLL + 4,
92 TranslationLL = SynchPtyErrOnTranslTableWalkLL + 4,
93 AccessFlagLL = TranslationLL + 4,
94 DomainLL = AccessFlagLL + 4,
95 PermissionLL = DomainLL + 4,
96 DebugEvent = PermissionLL + 4,
97 SynchronousExternalAbort,
98 TLBConflictAbort, // Requires LPAE
99 SynchPtyErrOnMemoryAccess,
100 AsynchronousExternalAbort,
101 AsynchPtyErrOnMemoryAccess,
102 AddressSizeLL, // AArch64 only
103
104 // Not real faults. These are faults to allow the translation function
105 // to inform the memory access function not to proceed for a prefetch
106 // that misses in the TLB or that targets an uncacheable address
107 PrefetchTLBMiss = AddressSizeLL + 4,
108 PrefetchUncacheable,
109
110 NumFaultSources,
111 FaultSourceInvalid = 0xff
112 };
113
114 /// Encodings of the fault sources when the short-desc. translation table
115 /// format is in use (ARM ARM Issue C B3.13.3)
116 static uint8_t shortDescFaultSources[NumFaultSources];
117 /// Encodings of the fault sources when the long-desc. translation table
118 /// format is in use (ARM ARM Issue C B3.13.3)
119 static uint8_t longDescFaultSources[NumFaultSources];
120 /// Encodings of the fault sources in AArch64 state
121 static uint8_t aarch64FaultSources[NumFaultSources];
122
123 enum AnnotationIDs
124 {
125 S1PTW, // DataAbort, PrefetchAbort: Stage 1 Page Table Walk,
126 OVA, // DataAbort, PrefetchAbort: stage 1 Virtual Address for stage 2 faults
127 SAS, // DataAbort: Syndrome Access Size
128 SSE, // DataAbort: Syndrome Sign Extend
129 SRT, // DataAbort: Syndrome Register Transfer
130
131 // AArch64 only
132 SF, // DataAbort: width of the accessed register is SixtyFour
133 AR // DataAbort: Acquire/Release semantics
134 };
135
136 enum TranMethod
137 {
138 LpaeTran,
139 VmsaTran,
140 UnknownTran
141 };
142
143 struct FaultVals
144 {
145 const FaultName name;
146
147 const FaultOffset offset;
148
149 // Offsets used for exceptions taken in AArch64 state
150 const uint16_t currELTOffset;
151 const uint16_t currELHOffset;
152 const uint16_t lowerEL64Offset;
153 const uint16_t lowerEL32Offset;
154
155 const OperatingMode nextMode;
156
157 const uint8_t armPcOffset;
158 const uint8_t thumbPcOffset;
159 // The following two values are used in place of armPcOffset and
160 // thumbPcOffset when the exception return address is saved into ELR
161 // registers (exceptions taken in HYP mode or in AArch64 state)
162 const uint8_t armPcElrOffset;
163 const uint8_t thumbPcElrOffset;
164
165 const bool hypTrappable;
166 const bool abortDisable;
167 const bool fiqDisable;
168
169 // Exception class used to appropriately set the syndrome register
170 // (exceptions taken in HYP mode or in AArch64 state)
171 const ExceptionClass ec;
172
173 FaultStat count;
174 FaultVals(const FaultName& name_, const FaultOffset& offset_,
175 const uint16_t& currELTOffset_, const uint16_t& currELHOffset_,
176 const uint16_t& lowerEL64Offset_,
177 const uint16_t& lowerEL32Offset_,
178 const OperatingMode& nextMode_, const uint8_t& armPcOffset_,
179 const uint8_t& thumbPcOffset_, const uint8_t& armPcElrOffset_,
180 const uint8_t& thumbPcElrOffset_, const bool& hypTrappable_,
181 const bool& abortDisable_, const bool& fiqDisable_,
182 const ExceptionClass& ec_)
183 : name(name_), offset(offset_), currELTOffset(currELTOffset_),
184 currELHOffset(currELHOffset_), lowerEL64Offset(lowerEL64Offset_),
185 lowerEL32Offset(lowerEL32Offset_), nextMode(nextMode_),
186 armPcOffset(armPcOffset_), thumbPcOffset(thumbPcOffset_),
187 armPcElrOffset(armPcElrOffset_), thumbPcElrOffset(thumbPcElrOffset_),
188 hypTrappable(hypTrappable_), abortDisable(abortDisable_),
189 fiqDisable(fiqDisable_), ec(ec_) {}
190 };
191
192 ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
193 machInst(_machInst), issRaw(_iss), from64(false), to64(false),
194 fromEL(EL0), toEL(EL0), fromMode(MODE_UNDEFINED), hypRouted(false) {}
195
196 // Returns the actual syndrome register to use based on the target
197 // exception level
198 MiscRegIndex getSyndromeReg64() const;
199 // Returns the actual fault address register to use based on the target
200 // exception level
201 MiscRegIndex getFaultAddrReg64() const;
202
203 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
204 StaticInst::nullStaticInstPtr) override;
205 void invoke64(ThreadContext *tc, const StaticInstPtr &inst =
206 StaticInst::nullStaticInstPtr);
207 virtual void annotate(AnnotationIDs id, uint64_t val) {}
208 virtual FaultStat& countStat() = 0;
209 virtual FaultOffset offset(ThreadContext *tc) = 0;
210 virtual FaultOffset offset64(ThreadContext *tc) = 0;
211 virtual OperatingMode nextMode() = 0;
212 virtual bool routeToMonitor(ThreadContext *tc) const = 0;
213 virtual bool routeToHyp(ThreadContext *tc) const { return false; }
214 virtual uint8_t armPcOffset(bool isHyp) = 0;
215 virtual uint8_t thumbPcOffset(bool isHyp) = 0;
216 virtual uint8_t armPcElrOffset() = 0;
217 virtual uint8_t thumbPcElrOffset() = 0;
218 virtual bool abortDisable(ThreadContext *tc) = 0;
219 virtual bool fiqDisable(ThreadContext *tc) = 0;
220 virtual ExceptionClass ec(ThreadContext *tc) const = 0;
221 virtual uint32_t iss() const = 0;
222 virtual bool isStage2() const { return false; }
223 virtual FSR getFsr(ThreadContext *tc) { return 0; }
224 virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg);
225};
226
227template<typename T>
228class ArmFaultVals : public ArmFault
229{
230 protected:
231 static FaultVals vals;
232
233 public:
234 ArmFaultVals<T>(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
235 ArmFault(_machInst, _iss) {}
236 FaultName name() const override { return vals.name; }
237 FaultStat & countStat() override { return vals.count; }
238 FaultOffset offset(ThreadContext *tc) override;
239
240 FaultOffset offset64(ThreadContext *tc) override;
241
242 OperatingMode nextMode() override { return vals.nextMode; }
243 virtual bool routeToMonitor(ThreadContext *tc) const override {
244 return false;
245 }
246 uint8_t armPcOffset(bool isHyp) override {
247 return isHyp ? vals.armPcElrOffset
248 : vals.armPcOffset;
249 }
250 uint8_t thumbPcOffset(bool isHyp) override {
251 return isHyp ? vals.thumbPcElrOffset
252 : vals.thumbPcOffset;
253 }
254 uint8_t armPcElrOffset() override { return vals.armPcElrOffset; }
255 uint8_t thumbPcElrOffset() override { return vals.thumbPcElrOffset; }
256 bool abortDisable(ThreadContext* tc) override { return vals.abortDisable; }
257 bool fiqDisable(ThreadContext* tc) override { return vals.fiqDisable; }
258 ExceptionClass ec(ThreadContext *tc) const override { return vals.ec; }
259 uint32_t iss() const override { return issRaw; }
260};
261
262class Reset : public ArmFaultVals<Reset>
263{
264 public:
265 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
266 StaticInst::nullStaticInstPtr) override;
267};
268
269class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
270{
271 protected:
272 bool unknown;
273 bool disabled;
274 ExceptionClass overrideEc;
275 const char *mnemonic;
276
277 public:
278 UndefinedInstruction(ExtMachInst _machInst,
279 bool _unknown,
280 const char *_mnemonic = NULL,
281 bool _disabled = false) :
282 ArmFaultVals<UndefinedInstruction>(_machInst),
283 unknown(_unknown), disabled(_disabled),
284 overrideEc(EC_INVALID), mnemonic(_mnemonic)
285 {}
286 UndefinedInstruction(ExtMachInst _machInst, uint32_t _iss,
287 ExceptionClass _overrideEc, const char *_mnemonic = NULL) :
288 ArmFaultVals<UndefinedInstruction>(_machInst, _iss),
289 unknown(false), disabled(true), overrideEc(_overrideEc),
290 mnemonic(_mnemonic)
291 {}
292
293 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
294 StaticInst::nullStaticInstPtr) override;
295 bool routeToHyp(ThreadContext *tc) const override;
296 ExceptionClass ec(ThreadContext *tc) const override;
297 uint32_t iss() const override;
298};
299
300class SupervisorCall : public ArmFaultVals<SupervisorCall>
301{
302 protected:
303 ExceptionClass overrideEc;
304 public:
305 SupervisorCall(ExtMachInst _machInst, uint32_t _iss,
306 ExceptionClass _overrideEc = EC_INVALID) :
307 ArmFaultVals<SupervisorCall>(_machInst, _iss),
308 overrideEc(_overrideEc)
309 {}
310
311 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
312 StaticInst::nullStaticInstPtr) override;
313 bool routeToHyp(ThreadContext *tc) const override;
314 ExceptionClass ec(ThreadContext *tc) const override;
315 uint32_t iss() const override;
316};
317
318class SecureMonitorCall : public ArmFaultVals<SecureMonitorCall>
319{
320 public:
321 SecureMonitorCall(ExtMachInst _machInst) :
322 ArmFaultVals<SecureMonitorCall>(_machInst)
323 {}
324
325 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
326 StaticInst::nullStaticInstPtr) override;
327 ExceptionClass ec(ThreadContext *tc) const override;
328 uint32_t iss() const override;
329};
330
331class SupervisorTrap : public ArmFaultVals<SupervisorTrap>
332{
333 protected:
334 ExtMachInst machInst;
335 ExceptionClass overrideEc;
336
337 public:
338 SupervisorTrap(ExtMachInst _machInst, uint32_t _iss,
339 ExceptionClass _overrideEc = EC_INVALID) :
340 ArmFaultVals<SupervisorTrap>(_machInst, _iss),
341 overrideEc(_overrideEc)
342 {}
343
344 bool routeToHyp(ThreadContext *tc) const override;
345 uint32_t iss() const override;
346 ExceptionClass ec(ThreadContext *tc) const override;
347};
348
349class SecureMonitorTrap : public ArmFaultVals<SecureMonitorTrap>
350{
351 protected:
352 ExtMachInst machInst;
353 ExceptionClass overrideEc;
354
355 public:
356 SecureMonitorTrap(ExtMachInst _machInst, uint32_t _iss,
357 ExceptionClass _overrideEc = EC_INVALID) :
358 ArmFaultVals<SecureMonitorTrap>(_machInst, _iss),
359 overrideEc(_overrideEc)
360 {}
361
362 ExceptionClass ec(ThreadContext *tc) const override;
363};
364
365class HypervisorCall : public ArmFaultVals<HypervisorCall>
366{
367 public:
368 HypervisorCall(ExtMachInst _machInst, uint32_t _imm);
369
370 ExceptionClass ec(ThreadContext *tc) const override;
371};
372
373class HypervisorTrap : public ArmFaultVals<HypervisorTrap>
374{
375 protected:
376 ExtMachInst machInst;
377 ExceptionClass overrideEc;
378
379 public:
380 HypervisorTrap(ExtMachInst _machInst, uint32_t _iss,
381 ExceptionClass _overrideEc = EC_INVALID) :
382 ArmFaultVals<HypervisorTrap>(_machInst, _iss),
383 overrideEc(_overrideEc)
384 {}
385
386 ExceptionClass ec(ThreadContext *tc) const override;
387};
388
389template <class T>
390class AbortFault : public ArmFaultVals<T>
391{
392 protected:
393 /**
394 * The virtual address the fault occured at. If 2 stages of
395 * translation are being used then this is the intermediate
396 * physical address that is the starting point for the second
397 * stage of translation.
398 */
399 Addr faultAddr;
400 /**
401 * Original virtual address. If the fault was generated on the
402 * second stage of translation then this variable stores the
403 * virtual address used in the original stage 1 translation.
404 */
405 Addr OVAddr;
406 bool write;
407 TlbEntry::DomainType domain;
408 uint8_t source;
409 uint8_t srcEncoded;
410 bool stage2;
411 bool s1ptw;
412 ArmFault::TranMethod tranMethod;
413
414 public:
415 AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain,
416 uint8_t _source, bool _stage2,
417 ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) :
418 faultAddr(_faultAddr), OVAddr(0), write(_write),
419 domain(_domain), source(_source), srcEncoded(0),
420 stage2(_stage2), s1ptw(false), tranMethod(_tranMethod)
421 {}
422
423 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
424 StaticInst::nullStaticInstPtr) override;
425
426 FSR getFsr(ThreadContext *tc) override;
427 bool abortDisable(ThreadContext *tc) override;
428 uint32_t iss() const override;
429 bool isStage2() const override { return stage2; }
430 void annotate(ArmFault::AnnotationIDs id, uint64_t val) override;
431 bool isMMUFault() const;
432};
433
434class PrefetchAbort : public AbortFault<PrefetchAbort>
435{
436 public:
437 static const MiscRegIndex FsrIndex = MISCREG_IFSR;
438 static const MiscRegIndex FarIndex = MISCREG_IFAR;
439 static const MiscRegIndex HFarIndex = MISCREG_HIFAR;
440
441 PrefetchAbort(Addr _addr, uint8_t _source, bool _stage2 = false,
442 ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) :
443 AbortFault<PrefetchAbort>(_addr, false, TlbEntry::DomainType::NoAccess,
444 _source, _stage2, _tranMethod)
445 {}
446
447 ExceptionClass ec(ThreadContext *tc) const override;
448 // @todo: external aborts should be routed if SCR.EA == 1
449 bool routeToMonitor(ThreadContext *tc) const override;
450 bool routeToHyp(ThreadContext *tc) const override;
451};
452
453class DataAbort : public AbortFault<DataAbort>
454{
455 public:
456 static const MiscRegIndex FsrIndex = MISCREG_DFSR;
457 static const MiscRegIndex FarIndex = MISCREG_DFAR;
458 static const MiscRegIndex HFarIndex = MISCREG_HDFAR;
459 bool isv;
460 uint8_t sas;
461 uint8_t sse;
462 uint8_t srt;
463
464 // AArch64 only
465 bool sf;
466 bool ar;
467
468 DataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source,
469 bool _stage2 = false, ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) :
470 AbortFault<DataAbort>(_addr, _write, _domain, _source, _stage2,
471 _tranMethod),
472 isv(false), sas (0), sse(0), srt(0), sf(false), ar(false)
473 {}
474
475 ExceptionClass ec(ThreadContext *tc) const override;
476 // @todo: external aborts should be routed if SCR.EA == 1
477 bool routeToMonitor(ThreadContext *tc) const override;
478 bool routeToHyp(ThreadContext *tc) const override;
479 uint32_t iss() const override;
480 void annotate(AnnotationIDs id, uint64_t val) override;
481};
482
483class VirtualDataAbort : public AbortFault<VirtualDataAbort>
484{
485 public:
486 static const MiscRegIndex FsrIndex = MISCREG_DFSR;
487 static const MiscRegIndex FarIndex = MISCREG_DFAR;
488 static const MiscRegIndex HFarIndex = MISCREG_HDFAR;
489
490 VirtualDataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write,
491 uint8_t _source) :
492 AbortFault<VirtualDataAbort>(_addr, _write, _domain, _source, false)
493 {}
494
495 void invoke(ThreadContext *tc, const StaticInstPtr &inst) override;
496};
497
498class Interrupt : public ArmFaultVals<Interrupt>
499{
500 public:
501 bool routeToMonitor(ThreadContext *tc) const override;
502 bool routeToHyp(ThreadContext *tc) const override;
503 bool abortDisable(ThreadContext *tc) override;
504};
505
506class VirtualInterrupt : public ArmFaultVals<VirtualInterrupt>
507{
508 public:
509 VirtualInterrupt();
510};
511
512class FastInterrupt : public ArmFaultVals<FastInterrupt>
513{
514 public:
515 bool routeToMonitor(ThreadContext *tc) const override;
516 bool routeToHyp(ThreadContext *tc) const override;
517 bool abortDisable(ThreadContext *tc) override;
518 bool fiqDisable(ThreadContext *tc) override;
519};
520
521class VirtualFastInterrupt : public ArmFaultVals<VirtualFastInterrupt>
522{
523 public:
524 VirtualFastInterrupt();
525};
526
527/// PC alignment fault (AArch64 only)
528class PCAlignmentFault : public ArmFaultVals<PCAlignmentFault>
529{
530 protected:
531 /// The unaligned value of the PC
532 Addr faultPC;
533 public:
534 PCAlignmentFault(Addr _faultPC) : faultPC(_faultPC)
535 {}
536 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
537 StaticInst::nullStaticInstPtr) override;
538 bool routeToHyp(ThreadContext *tc) const override;
539};
540
541/// Stack pointer alignment fault (AArch64 only)
542class SPAlignmentFault : public ArmFaultVals<SPAlignmentFault>
543{
544 public:
545 SPAlignmentFault();
546};
547
548/// System error (AArch64 only)
549class SystemError : public ArmFaultVals<SystemError>
550{
551 public:
552 SystemError();
553 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
554 StaticInst::nullStaticInstPtr) override;
555 bool routeToMonitor(ThreadContext *tc) const override;
556 bool routeToHyp(ThreadContext *tc) const override;
557};
558
559/// System error (AArch64 only)
560class SoftwareBreakpoint : public ArmFaultVals<SoftwareBreakpoint>
561{
562 public:
563 SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss);
564
565 bool routeToHyp(ThreadContext *tc) const override;
566};
567
568// A fault that flushes the pipe, excluding the faulting instructions
569class ArmSev : public ArmFaultVals<ArmSev>
570{
571 public:
572 ArmSev () {}
573 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
574 StaticInst::nullStaticInstPtr) override;
575};
576
577/// Illegal Instruction Set State fault (AArch64 only)
578class IllegalInstSetStateFault : public ArmFaultVals<IllegalInstSetStateFault>
579{
580 public:
581 IllegalInstSetStateFault();
582};
583
584/*
585 * Explicitly declare template static member variables to avoid warnings
586 * in some clang versions
587 */
588template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals;
589template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals;
590template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals;
591template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals;
592template<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals;
593template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals;
594template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals;
595template<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals;
596template<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals;
597template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals;
598template<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals;
599template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals;
600template<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals;
601template<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals;
602template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals;
603template<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals;
604template<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals;
605template<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals;
606template<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals;
607template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals;
608
609
610} // namespace ArmISA
611
612#endif // __ARM_FAULTS_HH__