1/*
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 * Gabe Black
43 * Giacomo Gabrielli
44 * Thomas Grocutt
45 */
46
47#ifndef __ARM_FAULTS_HH__
48#define __ARM_FAULTS_HH__
49
50#include "arch/arm/miscregs.hh"
51#include "arch/arm/pagetable.hh"
52#include "arch/arm/types.hh"
53#include "base/misc.hh"
54#include "sim/faults.hh"
55#include "sim/full_system.hh"
56
57// The design of the "name" and "vect" functions is in sim/faults.hh
58
59namespace ArmISA
60{
61typedef Addr FaultOffset;
62
63class ArmFault : public FaultBase
64{
65 protected:
66 ExtMachInst machInst;
67 uint32_t issRaw;
68
69 // Helper variables for ARMv8 exception handling
70 bool from64; // True if the exception is generated from the AArch64 state
71 bool to64; // True if the exception is taken in AArch64 state
72 ExceptionLevel fromEL; // Source exception level
73 ExceptionLevel toEL; // Target exception level
74 OperatingMode fromMode; // Source operating mode
75
76 Addr getVector(ThreadContext *tc);
77 Addr getVector64(ThreadContext *tc);
78
79 public:
80 /// Generic fault source enums used to index into
81 /// {short/long/aarch64}DescFaultSources[] to get the actual encodings based
82 /// on the current register width state and the translation table format in
83 /// use
84 enum FaultSource
85 {
86 AlignmentFault = 0,
87 InstructionCacheMaintenance, // Short-desc. format only
88 SynchExtAbtOnTranslTableWalkLL,
89 SynchPtyErrOnTranslTableWalkLL = SynchExtAbtOnTranslTableWalkLL + 4,
90 TranslationLL = SynchPtyErrOnTranslTableWalkLL + 4,
91 AccessFlagLL = TranslationLL + 4,
92 DomainLL = AccessFlagLL + 4,
93 PermissionLL = DomainLL + 4,
94 DebugEvent = PermissionLL + 4,
95 SynchronousExternalAbort,
96 TLBConflictAbort, // Requires LPAE
97 SynchPtyErrOnMemoryAccess,
98 AsynchronousExternalAbort,
99 AsynchPtyErrOnMemoryAccess,
100 AddressSizeLL, // AArch64 only
101
102 // Not real faults. These are faults to allow the translation function
103 // to inform the memory access function not to proceed for a prefetch
104 // that misses in the TLB or that targets an uncacheable address
105 PrefetchTLBMiss = AddressSizeLL + 4,
106 PrefetchUncacheable,
107
108 NumFaultSources,
109 FaultSourceInvalid = 0xff
110 };
111
112 /// Encodings of the fault sources when the short-desc. translation table
113 /// format is in use (ARM ARM Issue C B3.13.3)
114 static uint8_t shortDescFaultSources[NumFaultSources];
115 /// Encodings of the fault sources when the long-desc. translation table
116 /// format is in use (ARM ARM Issue C B3.13.3)
117 static uint8_t longDescFaultSources[NumFaultSources];
118 /// Encodings of the fault sources in AArch64 state
119 static uint8_t aarch64FaultSources[NumFaultSources];
120
121 enum AnnotationIDs
122 {
123 S1PTW, // DataAbort, PrefetchAbort: Stage 1 Page Table Walk,
124 OVA, // DataAbort, PrefetchAbort: stage 1 Virtual Address for stage 2 faults
125 SAS, // DataAbort: Syndrome Access Size
126 SSE, // DataAbort: Syndrome Sign Extend
127 SRT, // DataAbort: Syndrome Register Transfer
128
129 // AArch64 only
130 SF, // DataAbort: width of the accessed register is SixtyFour
131 AR // DataAbort: Acquire/Release semantics
132 };
133
134 enum TranMethod
135 {
136 LpaeTran,
137 VmsaTran,
138 UnknownTran
139 };
140
141 struct FaultVals
142 {
143 const FaultName name;
144
145 const FaultOffset offset;
146
147 // Offsets used for exceptions taken in AArch64 state
148 const uint16_t currELTOffset;
149 const uint16_t currELHOffset;
150 const uint16_t lowerEL64Offset;
151 const uint16_t lowerEL32Offset;
152
153 const OperatingMode nextMode;
154
155 const uint8_t armPcOffset;
156 const uint8_t thumbPcOffset;
157 // The following two values are used in place of armPcOffset and
158 // thumbPcOffset when the exception return address is saved into ELR
159 // registers (exceptions taken in HYP mode or in AArch64 state)
160 const uint8_t armPcElrOffset;
161 const uint8_t thumbPcElrOffset;
162
163 const bool hypTrappable;
164 const bool abortDisable;
165 const bool fiqDisable;
166
167 // Exception class used to appropriately set the syndrome register
168 // (exceptions taken in HYP mode or in AArch64 state)
169 const ExceptionClass ec;
170
171 FaultStat count;
172 };
173
174 ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
175 machInst(_machInst), issRaw(_iss), from64(false), to64(false),
176 fromEL(EL0), toEL(EL0), fromMode(MODE_UNDEFINED) {}
177
178 // Returns the actual syndrome register to use based on the target
179 // exception level
180 MiscRegIndex getSyndromeReg64() const;
181 // Returns the actual fault address register to use based on the target
182 // exception level
183 MiscRegIndex getFaultAddrReg64() const;
184
185 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
186 StaticInst::nullStaticInstPtr);
187 void invoke64(ThreadContext *tc, const StaticInstPtr &inst =
188 StaticInst::nullStaticInstPtr);
189 virtual void annotate(AnnotationIDs id, uint64_t val) {}
190 virtual FaultStat& countStat() = 0;
191 virtual FaultOffset offset(ThreadContext *tc) = 0;
192 virtual FaultOffset offset64() = 0;
193 virtual OperatingMode nextMode() = 0;
194 virtual bool routeToMonitor(ThreadContext *tc) const = 0;
195 virtual bool routeToHyp(ThreadContext *tc) const { return false; }
196 virtual uint8_t armPcOffset(bool isHyp) = 0;
197 virtual uint8_t thumbPcOffset(bool isHyp) = 0;
198 virtual uint8_t armPcElrOffset() = 0;
199 virtual uint8_t thumbPcElrOffset() = 0;
200 virtual bool abortDisable(ThreadContext *tc) = 0;
201 virtual bool fiqDisable(ThreadContext *tc) = 0;
202 virtual ExceptionClass ec(ThreadContext *tc) const = 0;
203 virtual uint32_t iss() const = 0;
204 virtual bool isStage2() const { return false; }
205 virtual FSR getFsr(ThreadContext *tc) { return 0; }
206 virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg);
207};
208
209template<typename T>
210class ArmFaultVals : public ArmFault
211{
212 protected:
213 static FaultVals vals;
214
215 public:
216 ArmFaultVals<T>(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
217 ArmFault(_machInst, _iss) {}
218 FaultName name() const { return vals.name; }
219 FaultStat & countStat() { return vals.count; }
220 FaultOffset offset(ThreadContext *tc);
221
222 FaultOffset
223 offset64()
224 {
225 if (toEL == fromEL) {
226 if (opModeIsT(fromMode))
227 return vals.currELTOffset;
228 return vals.currELHOffset;
229 } else {
230 if (from64)
231 return vals.lowerEL64Offset;
232 return vals.lowerEL32Offset;
233 }
234 }
235
236 OperatingMode nextMode() { return vals.nextMode; }
237 virtual bool routeToMonitor(ThreadContext *tc) const { return false; }
238 uint8_t armPcOffset(bool isHyp) { return isHyp ? vals.armPcElrOffset
239 : vals.armPcOffset; }
240 uint8_t thumbPcOffset(bool isHyp) { return isHyp ? vals.thumbPcElrOffset
241 : vals.thumbPcOffset; }
242 uint8_t armPcElrOffset() { return vals.armPcElrOffset; }
243 uint8_t thumbPcElrOffset() { return vals.thumbPcElrOffset; }
244 virtual bool abortDisable(ThreadContext* tc) { return vals.abortDisable; }
245 virtual bool fiqDisable(ThreadContext* tc) { return vals.fiqDisable; }
246 virtual ExceptionClass ec(ThreadContext *tc) const { return vals.ec; }
247 virtual uint32_t iss() const { return issRaw; }
248};
249
250class Reset : public ArmFaultVals<Reset>
251{
252 public:
253 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
254 StaticInst::nullStaticInstPtr);
255};
256
257class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
258{
259 protected:
260 bool unknown;
261 bool disabled;
262 ExceptionClass overrideEc;
263 const char *mnemonic;
264
265 public:
266 UndefinedInstruction(ExtMachInst _machInst,
267 bool _unknown,
268 const char *_mnemonic = NULL,
269 bool _disabled = false) :
270 ArmFaultVals<UndefinedInstruction>(_machInst),
271 unknown(_unknown), disabled(_disabled),
272 overrideEc(EC_INVALID), mnemonic(_mnemonic)
273 {}
274 UndefinedInstruction(ExtMachInst _machInst, uint32_t _iss,
275 ExceptionClass _overrideEc, const char *_mnemonic = NULL) :
276 ArmFaultVals<UndefinedInstruction>(_machInst, _iss),
277 unknown(false), disabled(true), overrideEc(_overrideEc),
278 mnemonic(_mnemonic)
279 {}
280
281 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
282 StaticInst::nullStaticInstPtr);
283 bool routeToHyp(ThreadContext *tc) const;
284 ExceptionClass ec(ThreadContext *tc) const;
285 uint32_t iss() const;
286};
287
288class SupervisorCall : public ArmFaultVals<SupervisorCall>
289{
290 protected:
291 ExceptionClass overrideEc;
292 public:
293 SupervisorCall(ExtMachInst _machInst, uint32_t _iss,
294 ExceptionClass _overrideEc = EC_INVALID) :
295 ArmFaultVals<SupervisorCall>(_machInst, _iss),
296 overrideEc(_overrideEc)
297 {}
298
299 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
300 StaticInst::nullStaticInstPtr);
301 bool routeToHyp(ThreadContext *tc) const;
302 ExceptionClass ec(ThreadContext *tc) const;
303 uint32_t iss() const;
304};
305
306class SecureMonitorCall : public ArmFaultVals<SecureMonitorCall>
307{
308 public:
309 SecureMonitorCall(ExtMachInst _machInst) :
310 ArmFaultVals<SecureMonitorCall>(_machInst)
311 {}
312
313 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
314 StaticInst::nullStaticInstPtr);
315 ExceptionClass ec(ThreadContext *tc) const;
316 uint32_t iss() const;
317};
318
319class SupervisorTrap : public ArmFaultVals<SupervisorTrap>
320{
321 protected:
322 ExtMachInst machInst;
323 ExceptionClass overrideEc;
324
325 public:
326 SupervisorTrap(ExtMachInst _machInst, uint32_t _iss,
327 ExceptionClass _overrideEc = EC_INVALID) :
328 ArmFaultVals<SupervisorTrap>(_machInst, _iss),
329 overrideEc(_overrideEc)
330 {}
331
332 ExceptionClass ec(ThreadContext *tc) const;
333};
334
335class SecureMonitorTrap : public ArmFaultVals<SecureMonitorTrap>
336{
337 protected:
338 ExtMachInst machInst;
339 ExceptionClass overrideEc;
340
341 public:
342 SecureMonitorTrap(ExtMachInst _machInst, uint32_t _iss,
343 ExceptionClass _overrideEc = EC_INVALID) :
344 ArmFaultVals<SecureMonitorTrap>(_machInst, _iss),
345 overrideEc(_overrideEc)
346 {}
347
348 ExceptionClass ec(ThreadContext *tc) const;
349};
350
351class HypervisorCall : public ArmFaultVals<HypervisorCall>
352{
353 public:
354 HypervisorCall(ExtMachInst _machInst, uint32_t _imm);
355};
356
357class HypervisorTrap : public ArmFaultVals<HypervisorTrap>
358{
359 protected:
360 ExtMachInst machInst;
361 ExceptionClass overrideEc;
362
363 public:
364 HypervisorTrap(ExtMachInst _machInst, uint32_t _iss,
365 ExceptionClass _overrideEc = EC_INVALID) :
366 ArmFaultVals<HypervisorTrap>(_machInst, _iss),
367 overrideEc(_overrideEc)
368 {}
369
370 ExceptionClass ec(ThreadContext *tc) const;
371};
372
373template <class T>
374class AbortFault : public ArmFaultVals<T>
375{
376 protected:
377 /**
378 * The virtual address the fault occured at. If 2 stages of
379 * translation are being used then this is the intermediate
380 * physical address that is the starting point for the second
381 * stage of translation.
382 */
383 Addr faultAddr;
384 /**
385 * Original virtual address. If the fault was generated on the
386 * second stage of translation then this variable stores the
387 * virtual address used in the original stage 1 translation.
388 */
389 Addr OVAddr;
390 bool write;
391 TlbEntry::DomainType domain;
392 uint8_t source;
393 uint8_t srcEncoded;
394 bool stage2;
395 bool s1ptw;
396 ArmFault::TranMethod tranMethod;
397
398 public:
399 AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain,
400 uint8_t _source, bool _stage2,
401 ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) :
402 faultAddr(_faultAddr), OVAddr(0), write(_write),
403 domain(_domain), source(_source), srcEncoded(0),
404 stage2(_stage2), s1ptw(false), tranMethod(_tranMethod)
405 {}
406
407 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
408 StaticInst::nullStaticInstPtr);
409
410 FSR getFsr(ThreadContext *tc);
411 bool abortDisable(ThreadContext *tc);
412 uint32_t iss() const;
413 bool isStage2() const { return stage2; }
414 void annotate(ArmFault::AnnotationIDs id, uint64_t val);
415 bool isMMUFault() const;
416};
417
418class PrefetchAbort : public AbortFault<PrefetchAbort>
419{
420 public:
421 static const MiscRegIndex FsrIndex = MISCREG_IFSR;
422 static const MiscRegIndex FarIndex = MISCREG_IFAR;
423 static const MiscRegIndex HFarIndex = MISCREG_HIFAR;
424
425 PrefetchAbort(Addr _addr, uint8_t _source, bool _stage2 = false,
426 ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) :
427 AbortFault<PrefetchAbort>(_addr, false, TlbEntry::DomainType::NoAccess,
428 _source, _stage2, _tranMethod)
429 {}
430
431 ExceptionClass ec(ThreadContext *tc) const;
432 // @todo: external aborts should be routed if SCR.EA == 1
433 bool routeToMonitor(ThreadContext *tc) const;
434 bool routeToHyp(ThreadContext *tc) const;
435};
436
437class DataAbort : public AbortFault<DataAbort>
438{
439 public:
440 static const MiscRegIndex FsrIndex = MISCREG_DFSR;
441 static const MiscRegIndex FarIndex = MISCREG_DFAR;
442 static const MiscRegIndex HFarIndex = MISCREG_HDFAR;
443 bool isv;
444 uint8_t sas;
445 uint8_t sse;
446 uint8_t srt;
447
448 // AArch64 only
449 bool sf;
450 bool ar;
451
452 DataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source,
453 bool _stage2 = false, ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) :
454 AbortFault<DataAbort>(_addr, _write, _domain, _source, _stage2,
455 _tranMethod),
456 isv(false), sas (0), sse(0), srt(0), sf(false), ar(false)
457 {}
458
459 ExceptionClass ec(ThreadContext *tc) const;
460 // @todo: external aborts should be routed if SCR.EA == 1
461 bool routeToMonitor(ThreadContext *tc) const;
462 bool routeToHyp(ThreadContext *tc) const;
463 uint32_t iss() const;
464 void annotate(AnnotationIDs id, uint64_t val);
465};
466
467class VirtualDataAbort : public AbortFault<VirtualDataAbort>
468{
469 public:
470 static const MiscRegIndex FsrIndex = MISCREG_DFSR;
471 static const MiscRegIndex FarIndex = MISCREG_DFAR;
472 static const MiscRegIndex HFarIndex = MISCREG_HDFAR;
473
474 VirtualDataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write,
475 uint8_t _source) :
476 AbortFault<VirtualDataAbort>(_addr, _write, _domain, _source, false)
477 {}
478
479 void invoke(ThreadContext *tc, const StaticInstPtr &inst);
480};
481
482class Interrupt : public ArmFaultVals<Interrupt>
483{
484 public:
485 bool routeToMonitor(ThreadContext *tc) const;
486 bool routeToHyp(ThreadContext *tc) const;
487 bool abortDisable(ThreadContext *tc);
488};
489
490class VirtualInterrupt : public ArmFaultVals<VirtualInterrupt>
491{
492 public:
493 VirtualInterrupt();
494};
495
496class FastInterrupt : public ArmFaultVals<FastInterrupt>
497{
498 public:
499 bool routeToMonitor(ThreadContext *tc) const;
500 bool routeToHyp(ThreadContext *tc) const;
501 bool abortDisable(ThreadContext *tc);
502 bool fiqDisable(ThreadContext *tc);
503};
504
505class VirtualFastInterrupt : public ArmFaultVals<VirtualFastInterrupt>
506{
507 public:
508 VirtualFastInterrupt();
509};
510
511/// PC alignment fault (AArch64 only)
512class PCAlignmentFault : public ArmFaultVals<PCAlignmentFault>
513{
514 protected:
515 /// The unaligned value of the PC
516 Addr faultPC;
517 public:
518 PCAlignmentFault(Addr _faultPC) : faultPC(_faultPC)
519 {}
520 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
521 StaticInst::nullStaticInstPtr);
522};
523
524/// Stack pointer alignment fault (AArch64 only)
525class SPAlignmentFault : public ArmFaultVals<SPAlignmentFault>
526{
527 public:
528 SPAlignmentFault();
529};
530
531/// System error (AArch64 only)
532class SystemError : public ArmFaultVals<SystemError>
533{
534 public:
535 SystemError();
536 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
537 StaticInst::nullStaticInstPtr);
538 bool routeToMonitor(ThreadContext *tc) const;
539 bool routeToHyp(ThreadContext *tc) const;
540};
541
542// A fault that flushes the pipe, excluding the faulting instructions
543class FlushPipe : public ArmFaultVals<FlushPipe>
544{
545 public:
546 FlushPipe() {}
547 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
548 StaticInst::nullStaticInstPtr);
549};
550
551// A fault that flushes the pipe, excluding the faulting instructions
552class ArmSev : public ArmFaultVals<ArmSev>
553{
554 public:
555 ArmSev () {}
556 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
557 StaticInst::nullStaticInstPtr);
558};
559
560/// Illegal Instruction Set State fault (AArch64 only)
561class IllegalInstSetStateFault : public ArmFaultVals<IllegalInstSetStateFault>
562{
563 public:
564 IllegalInstSetStateFault();
565};
566
567} // namespace ArmISA
568
569#endif // __ARM_FAULTS_HH__