faults.cc (8314:13ac7b9939ef) | faults.cc (8518:9c87727099ce) |
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1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 64 unchanged lines hidden (view full) --- 73 {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true}; 74 75template<> ArmFault::FaultVals ArmFaultVals<FlushPipe>::vals = 76 {"Pipe Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values 77 78template<> ArmFault::FaultVals ArmFaultVals<ReExec>::vals = 79 {"ReExec Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values 80 | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 64 unchanged lines hidden (view full) --- 73 {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true}; 74 75template<> ArmFault::FaultVals ArmFaultVals<FlushPipe>::vals = 76 {"Pipe Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values 77 78template<> ArmFault::FaultVals ArmFaultVals<ReExec>::vals = 79 {"ReExec Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values 80 |
81template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals = 82 {"ArmSev Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values |
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81Addr 82ArmFault::getVector(ThreadContext *tc) 83{ 84 // ARM ARM B1-3 85 86 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 87 88 // panic if SCTLR.VE because I have no idea what to do with vectored --- 33 unchanged lines hidden (view full) --- 122 cpsr.j = 0; 123 124 cpsr.t = sctlr.te; 125 cpsr.a = cpsr.a | abortDisable(); 126 cpsr.f = cpsr.f | fiqDisable(); 127 cpsr.i = 1; 128 cpsr.e = sctlr.ee; 129 tc->setMiscReg(MISCREG_CPSR, cpsr); | 83Addr 84ArmFault::getVector(ThreadContext *tc) 85{ 86 // ARM ARM B1-3 87 88 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 89 90 // panic if SCTLR.VE because I have no idea what to do with vectored --- 33 unchanged lines hidden (view full) --- 124 cpsr.j = 0; 125 126 cpsr.t = sctlr.te; 127 cpsr.a = cpsr.a | abortDisable(); 128 cpsr.f = cpsr.f | fiqDisable(); 129 cpsr.i = 1; 130 cpsr.e = sctlr.ee; 131 tc->setMiscReg(MISCREG_CPSR, cpsr); |
132 // Make sure mailbox sets to one always 133 tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); |
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130 tc->setIntReg(INTREG_LR, curPc + 131 (saved_cpsr.t ? thumbPcOffset() : armPcOffset())); 132 133 switch (nextMode()) { 134 case MODE_FIQ: 135 tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr); 136 break; 137 case MODE_IRQ: --- 109 unchanged lines hidden (view full) --- 247 tc->pcState(pc); 248} 249 250template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc, 251 StaticInstPtr inst); 252template void AbortFault<DataAbort>::invoke(ThreadContext *tc, 253 StaticInstPtr inst); 254 | 134 tc->setIntReg(INTREG_LR, curPc + 135 (saved_cpsr.t ? thumbPcOffset() : armPcOffset())); 136 137 switch (nextMode()) { 138 case MODE_FIQ: 139 tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr); 140 break; 141 case MODE_IRQ: --- 109 unchanged lines hidden (view full) --- 251 tc->pcState(pc); 252} 253 254template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc, 255 StaticInstPtr inst); 256template void AbortFault<DataAbort>::invoke(ThreadContext *tc, 257 StaticInstPtr inst); 258 |
259void 260ArmSev::invoke(ThreadContext *tc, StaticInstPtr inst) { 261 DPRINTF(Faults, "Invoking ArmSev Fault\n"); 262#if FULL_SYSTEM 263 // Set sev_mailbox to 1, clear the pending interrupt from remote 264 // SEV execution and let pipeline continue as pcState is still 265 // valid. 266 tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 267 tc->getCpuPtr()->clearInterrupt(INT_SEV, 0); 268#endif 269} 270 |
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255// return via SUBS pc, lr, xxx; rfe, movs, ldm 256 257} // namespace ArmISA | 271// return via SUBS pc, lr, xxx; rfe, movs, ldm 272 273} // namespace ArmISA |