faults.cc (8232:b28d06a175be) faults.cc (8301:858384f3af1c)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 93 unchanged lines hidden (view full) ---

102{
103 // ARM ARM B1.6.3
104 FaultBase::invoke(tc);
105 countStat()++;
106
107 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
108 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
109 CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) |
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 93 unchanged lines hidden (view full) ---

102{
103 // ARM ARM B1.6.3
104 FaultBase::invoke(tc);
105 countStat()++;
106
107 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
108 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
109 CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) |
110 tc->readIntReg(INTREG_CONDCODES);
110 tc->readIntReg(INTREG_CONDCODES_F) |
111 tc->readIntReg(INTREG_CONDCODES_Q) |
112 tc->readIntReg(INTREG_CONDCODES_GE);
111 Addr curPc M5_VAR_USED = tc->pcState().pc();
112 ITSTATE it = tc->pcState().itstate();
113 saved_cpsr.it2 = it.top6;
114 saved_cpsr.it1 = it.bottom2;
115
116 cpsr.mode = nextMode();
117 cpsr.it1 = cpsr.it2 = 0;
118 cpsr.j = 0;

--- 133 unchanged lines hidden --- 		113 Addr curPc M5_VAR_USED = tc->pcState().pc();
114 ITSTATE it = tc->pcState().itstate();
115 saved_cpsr.it2 = it.top6;
116 saved_cpsr.it1 = it.bottom2;
117
118 cpsr.mode = nextMode();
119 cpsr.it1 = cpsr.it2 = 0;
120 cpsr.j = 0;

--- 133 unchanged lines hidden ---