faults.cc (8202:1b63e9afeafc) faults.cc (8205:7ecbffb674aa)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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103 FaultBase::invoke(tc);
104 countStat()++;
105
106 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
107 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
108 CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) |
109 tc->readIntReg(INTREG_CONDCODES);
110 Addr curPc M5_VAR_USED = tc->pcState().pc();
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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103 FaultBase::invoke(tc);
104 countStat()++;
105
106 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
107 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
108 CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) |
109 tc->readIntReg(INTREG_CONDCODES);
110 Addr curPc M5_VAR_USED = tc->pcState().pc();
111
111 ITSTATE it = tc->pcState().itstate();
112 saved_cpsr.it2 = it.top6;
113 saved_cpsr.it1 = it.bottom2;
112
113 cpsr.mode = nextMode();
114 cpsr.it1 = cpsr.it2 = 0;
115 cpsr.j = 0;
116
117 cpsr.t = sctlr.te;
118 cpsr.a = cpsr.a | abortDisable();
119 cpsr.f = cpsr.f | fiqDisable();

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154 tc->pcState(pc);
155}
156
157void
158Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
159{
160 tc->getCpuPtr()->clearInterrupts();
161 tc->clearArchRegs();
114
115 cpsr.mode = nextMode();
116 cpsr.it1 = cpsr.it2 = 0;
117 cpsr.j = 0;
118
119 cpsr.t = sctlr.te;
120 cpsr.a = cpsr.a | abortDisable();
121 cpsr.f = cpsr.f | fiqDisable();

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156 tc->pcState(pc);
157}
158
159void
160Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
161{
162 tc->getCpuPtr()->clearInterrupts();
163 tc->clearArchRegs();
162 ArmFault::invoke(tc);
164 ArmFault::invoke(tc, inst);
163}
164
165#else
166
167void
168UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
169{
170 // If the mnemonic isn't defined this has to be an unknown instruction.

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198}
199
200#endif // FULL_SYSTEM
201
202template<class T>
203void
204AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
205{
165}
166
167#else
168
169void
170UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
171{
172 // If the mnemonic isn't defined this has to be an unknown instruction.

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200}
201
202#endif // FULL_SYSTEM
203
204template<class T>
205void
206AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
207{
206 ArmFaultVals::invoke(tc);
208 ArmFaultVals<T>::invoke(tc, inst);
207 FSR fsr = 0;
208 fsr.fsLow = bits(status, 3, 0);
209 fsr.fsHigh = bits(status, 4);
210 fsr.domain = domain;
211 fsr.wnr = (write ? 1 : 0);
212 fsr.ext = 0;
213 tc->setMiscReg(T::FsrIndex, fsr);
214 tc->setMiscReg(T::FarIndex, faultAddr);
215}
216
217void
218FlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) {
219 DPRINTF(Faults, "Invoking FlushPipe Fault\n");
220
221 // Set the PC to the next instruction of the faulting instruction.
222 // Net effect is simply squashing all instructions behind and
223 // start refetching from the next instruction.
224 PCState pc = tc->pcState();
225 assert(inst);
209 FSR fsr = 0;
210 fsr.fsLow = bits(status, 3, 0);
211 fsr.fsHigh = bits(status, 4);
212 fsr.domain = domain;
213 fsr.wnr = (write ? 1 : 0);
214 fsr.ext = 0;
215 tc->setMiscReg(T::FsrIndex, fsr);
216 tc->setMiscReg(T::FarIndex, faultAddr);
217}
218
219void
220FlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) {
221 DPRINTF(Faults, "Invoking FlushPipe Fault\n");
222
223 // Set the PC to the next instruction of the faulting instruction.
224 // Net effect is simply squashing all instructions behind and
225 // start refetching from the next instruction.
226 PCState pc = tc->pcState();
227 assert(inst);
226 pc.forcedItState(inst->machInst.newItstate);
227 inst->advancePC(pc);
228 tc->pcState(pc);
229}
230
231void
232ReExec::invoke(ThreadContext *tc, StaticInstPtr inst) {
233 DPRINTF(Faults, "Invoking ReExec Fault\n");
234

--- 15 unchanged lines hidden --- 		228 inst->advancePC(pc);
229 tc->pcState(pc);
230}
231
232void
233ReExec::invoke(ThreadContext *tc, StaticInstPtr inst) {
234 DPRINTF(Faults, "Invoking ReExec Fault\n");
235

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