faults.cc (7692:8173327c9c65) faults.cc (7720:65d338a8dba4)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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99 // ARM ARM B1.6.3
100 FaultBase::invoke(tc);
101 countStat()++;
102
103 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
104 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
105 CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) |
106 tc->readIntReg(INTREG_CONDCODES);
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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99 // ARM ARM B1.6.3
100 FaultBase::invoke(tc);
101 countStat()++;
102
103 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
104 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
105 CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) |
106 tc->readIntReg(INTREG_CONDCODES);
107 Addr curPc M5_VAR_USED = tc->pcState().pc();
107
108
109 cpsr.mode = nextMode();
110 cpsr.it1 = cpsr.it2 = 0;
111 cpsr.j = 0;
112
113 cpsr.t = sctlr.te;
114 cpsr.a = cpsr.a | abortDisable();
115 cpsr.f = cpsr.f | fiqDisable();
116 cpsr.i = 1;
117 cpsr.e = sctlr.ee;
118 tc->setMiscReg(MISCREG_CPSR, cpsr);
108
109
110 cpsr.mode = nextMode();
111 cpsr.it1 = cpsr.it2 = 0;
112 cpsr.j = 0;
113
114 cpsr.t = sctlr.te;
115 cpsr.a = cpsr.a | abortDisable();
116 cpsr.f = cpsr.f | fiqDisable();
117 cpsr.i = 1;
118 cpsr.e = sctlr.ee;
119 tc->setMiscReg(MISCREG_CPSR, cpsr);
119 tc->setIntReg(INTREG_LR, tc->readPC() +
120 tc->setIntReg(INTREG_LR, curPc +
120 (saved_cpsr.t ? thumbPcOffset() : armPcOffset()));
121
122 switch (nextMode()) {
123 case MODE_FIQ:
124 tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
125 break;
126 case MODE_IRQ:
127 tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);

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134 break;
135 case MODE_ABORT:
136 tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
137 break;
138 default:
139 panic("unknown Mode\n");
140 }
141
121 (saved_cpsr.t ? thumbPcOffset() : armPcOffset()));
122
123 switch (nextMode()) {
124 case MODE_FIQ:
125 tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
126 break;
127 case MODE_IRQ:
128 tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);

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135 break;
136 case MODE_ABORT:
137 tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
138 break;
139 default:
140 panic("unknown Mode\n");
141 }
142
142 Addr pc M5_VAR_USED = tc->readPC();
143 Addr newPc = getVector(tc) | (sctlr.te ? PcTBit : 0);
143 Addr newPc = getVector(tc);
144 DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
144 DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
145 name(), cpsr, pc, tc->readIntReg(INTREG_LR), newPc);
146 tc->setPC(newPc);
147 tc->setNextPC(newPc + cpsr.t ? 2 : 4 );
148 tc->setMicroPC(0);
149 tc->setNextMicroPC(1);
145 name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc);
146 PCState pc(newPc);
147 pc.thumb(cpsr.t);
148 pc.nextThumb(pc.thumb());
149 pc.jazelle(cpsr.j);
150 pc.nextJazelle(pc.jazelle());
151 tc->pcState(pc);
150}
151
152void
153Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
154{
155 tc->getCpuPtr()->clearInterrupts();
156 tc->clearArchRegs();
157 ArmFault::invoke(tc);

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188 callNum = bits(machInst, 23, 0);
189 }
190 if (callNum == 0) {
191 callNum = tc->readIntReg(INTREG_R7);
192 }
193 tc->syscall(callNum);
194
195 // Advance the PC since that won't happen automatically.
152}
153
154void
155Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
156{
157 tc->getCpuPtr()->clearInterrupts();
158 tc->clearArchRegs();
159 ArmFault::invoke(tc);

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190 callNum = bits(machInst, 23, 0);
191 }
192 if (callNum == 0) {
193 callNum = tc->readIntReg(INTREG_R7);
194 }
195 tc->syscall(callNum);
196
197 // Advance the PC since that won't happen automatically.
196 tc->setPC(tc->readNextPC());
197 tc->setNextPC(tc->readNextNPC());
198 tc->setMicroPC(0);
199 tc->setNextMicroPC(1);
198 PCState pc = tc->pcState();
199 assert(inst);
200 inst->advancePC(pc);
201 tc->pcState(pc);
200}
201
202#endif // FULL_SYSTEM
203
204template<class T>
205void
206AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
207{

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218
219void
220FlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) {
221 DPRINTF(Faults, "Invoking FlushPipe Fault\n");
222
223 // Set the PC to the next instruction of the faulting instruction.
224 // Net effect is simply squashing all instructions behind and
225 // start refetching from the next instruction.
202}
203
204#endif // FULL_SYSTEM
205
206template<class T>
207void
208AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
209{

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220
221void
222FlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) {
223 DPRINTF(Faults, "Invoking FlushPipe Fault\n");
224
225 // Set the PC to the next instruction of the faulting instruction.
226 // Net effect is simply squashing all instructions behind and
227 // start refetching from the next instruction.
226 tc->setPC(tc->readNextPC());
227 tc->setNextPC(tc->readNextNPC());
228 tc->setMicroPC(0);
229 tc->setNextMicroPC(1);
228 PCState pc = tc->pcState();
229 assert(inst);
230 inst->advancePC(pc);
231 tc->pcState(pc);
230}
231
232template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc,
233 StaticInstPtr inst);
234template void AbortFault<DataAbort>::invoke(ThreadContext *tc,
235 StaticInstPtr inst);
236
237// return via SUBS pc, lr, xxx; rfe, movs, ldm
238
239} // namespace ArmISA
232}
233
234template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc,
235 StaticInstPtr inst);
236template void AbortFault<DataAbort>::invoke(ThreadContext *tc,
237 StaticInstPtr inst);
238
239// return via SUBS pc, lr, xxx; rfe, movs, ldm
240
241} // namespace ArmISA