faults.cc (7678:f19b6a3a8cec) faults.cc (7692:8173327c9c65)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 126 unchanged lines hidden (view full) ---

135 case MODE_ABORT:
136 tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
137 break;
138 default:
139 panic("unknown Mode\n");
140 }
141
142 Addr pc M5_VAR_USED = tc->readPC();
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 126 unchanged lines hidden (view full) ---

135 case MODE_ABORT:
136 tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
137 break;
138 default:
139 panic("unknown Mode\n");
140 }
141
142 Addr pc M5_VAR_USED = tc->readPC();
143 Addr newPc = getVector(tc) | (sctlr.te ? (ULL(1) << PcTBitShift) : 0);
143 Addr newPc = getVector(tc) | (sctlr.te ? PcTBit : 0);
144 DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
145 name(), cpsr, pc, tc->readIntReg(INTREG_LR), newPc);
146 tc->setPC(newPc);
147 tc->setNextPC(newPc + cpsr.t ? 2 : 4 );
148 tc->setMicroPC(0);
149 tc->setNextMicroPC(1);
150}
151

--- 88 unchanged lines hidden --- 		144 DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
145 name(), cpsr, pc, tc->readIntReg(INTREG_LR), newPc);
146 tc->setPC(newPc);
147 tc->setNextPC(newPc + cpsr.t ? 2 : 4 );
148 tc->setMicroPC(0);
149 tc->setNextMicroPC(1);
150}
151

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