faults.cc (7652:f2621206b062) | faults.cc (7678:f19b6a3a8cec) |
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1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 80 unchanged lines hidden (view full) --- 89 return offset(); 90 return offset() + HighVecs; 91 92} 93 94#if FULL_SYSTEM 95 96void | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 80 unchanged lines hidden (view full) --- 89 return offset(); 90 return offset() + HighVecs; 91 92} 93 94#if FULL_SYSTEM 95 96void |
97ArmFault::invoke(ThreadContext *tc) | 97ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst) |
98{ 99 // ARM ARM B1.6.3 100 FaultBase::invoke(tc); 101 countStat()++; 102 103 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 104 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 105 CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) | --- 39 unchanged lines hidden (view full) --- 145 name(), cpsr, pc, tc->readIntReg(INTREG_LR), newPc); 146 tc->setPC(newPc); 147 tc->setNextPC(newPc + cpsr.t ? 2 : 4 ); 148 tc->setMicroPC(0); 149 tc->setNextMicroPC(1); 150} 151 152void | 98{ 99 // ARM ARM B1.6.3 100 FaultBase::invoke(tc); 101 countStat()++; 102 103 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 104 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 105 CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) | --- 39 unchanged lines hidden (view full) --- 145 name(), cpsr, pc, tc->readIntReg(INTREG_LR), newPc); 146 tc->setPC(newPc); 147 tc->setNextPC(newPc + cpsr.t ? 2 : 4 ); 148 tc->setMicroPC(0); 149 tc->setNextMicroPC(1); 150} 151 152void |
153Reset::invoke(ThreadContext *tc) | 153Reset::invoke(ThreadContext *tc, StaticInstPtr inst) |
154{ 155 tc->getCpuPtr()->clearInterrupts(); 156 tc->clearArchRegs(); 157 ArmFault::invoke(tc); 158} 159 160#else 161 162void | 154{ 155 tc->getCpuPtr()->clearInterrupts(); 156 tc->clearArchRegs(); 157 ArmFault::invoke(tc); 158} 159 160#else 161 162void |
163UndefinedInstruction::invoke(ThreadContext *tc) | 163UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst) |
164{ 165 // If the mnemonic isn't defined this has to be an unknown instruction. 166 assert(unknown || mnemonic != NULL); 167 if (disabled) { 168 panic("Attempted to execute disabled instruction " 169 "'%s' (inst 0x%08x)", mnemonic, machInst); 170 } else if (unknown) { 171 panic("Attempted to execute unknown instruction (inst 0x%08x)", 172 machInst); 173 } else { 174 panic("Attempted to execute unimplemented instruction " 175 "'%s' (inst 0x%08x)", mnemonic, machInst); 176 } 177} 178 179void | 164{ 165 // If the mnemonic isn't defined this has to be an unknown instruction. 166 assert(unknown || mnemonic != NULL); 167 if (disabled) { 168 panic("Attempted to execute disabled instruction " 169 "'%s' (inst 0x%08x)", mnemonic, machInst); 170 } else if (unknown) { 171 panic("Attempted to execute unknown instruction (inst 0x%08x)", 172 machInst); 173 } else { 174 panic("Attempted to execute unimplemented instruction " 175 "'%s' (inst 0x%08x)", mnemonic, machInst); 176 } 177} 178 179void |
180SupervisorCall::invoke(ThreadContext *tc) | 180SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst) |
181{ 182 // As of now, there isn't a 32 bit thumb version of this instruction. 183 assert(!machInst.bigThumb); 184 uint32_t callNum; 185 if (machInst.thumb) { 186 callNum = bits(machInst, 7, 0); 187 } else { 188 callNum = bits(machInst, 23, 0); --- 9 unchanged lines hidden (view full) --- 198 tc->setMicroPC(0); 199 tc->setNextMicroPC(1); 200} 201 202#endif // FULL_SYSTEM 203 204template<class T> 205void | 181{ 182 // As of now, there isn't a 32 bit thumb version of this instruction. 183 assert(!machInst.bigThumb); 184 uint32_t callNum; 185 if (machInst.thumb) { 186 callNum = bits(machInst, 7, 0); 187 } else { 188 callNum = bits(machInst, 23, 0); --- 9 unchanged lines hidden (view full) --- 198 tc->setMicroPC(0); 199 tc->setNextMicroPC(1); 200} 201 202#endif // FULL_SYSTEM 203 204template<class T> 205void |
206AbortFault | 206AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst) |
207{ 208 ArmFaultVals<T>::invoke(tc); 209 FSR fsr = 0; 210 fsr.fsLow = bits(status, 3, 0); 211 fsr.fsHigh = bits(status, 4); 212 fsr.domain = domain; 213 fsr.wnr = (write ? 1 : 0); 214 fsr.ext = 0; 215 tc->setMiscReg(T::FsrIndex, fsr); 216 tc->setMiscReg(T::FarIndex, faultAddr); 217} 218 219void | 207{ 208 ArmFaultVals<T>::invoke(tc); 209 FSR fsr = 0; 210 fsr.fsLow = bits(status, 3, 0); 211 fsr.fsHigh = bits(status, 4); 212 fsr.domain = domain; 213 fsr.wnr = (write ? 1 : 0); 214 fsr.ext = 0; 215 tc->setMiscReg(T::FsrIndex, fsr); 216 tc->setMiscReg(T::FarIndex, faultAddr); 217} 218 219void |
220FlushPipe::invoke(ThreadContext *tc) { | 220FlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) { |
221 DPRINTF(Faults, "Invoking FlushPipe Fault\n"); 222 223 // Set the PC to the next instruction of the faulting instruction. 224 // Net effect is simply squashing all instructions behind and 225 // start refetching from the next instruction. 226 tc->setPC(tc->readNextPC()); 227 tc->setNextPC(tc->readNextNPC()); 228 tc->setMicroPC(0); 229 tc->setNextMicroPC(1); 230} 231 | 221 DPRINTF(Faults, "Invoking FlushPipe Fault\n"); 222 223 // Set the PC to the next instruction of the faulting instruction. 224 // Net effect is simply squashing all instructions behind and 225 // start refetching from the next instruction. 226 tc->setPC(tc->readNextPC()); 227 tc->setNextPC(tc->readNextNPC()); 228 tc->setMicroPC(0); 229 tc->setNextMicroPC(1); 230} 231 |
232template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc); 233template void AbortFault<DataAbort>::invoke(ThreadContext *tc); | 232template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc, 233 StaticInstPtr inst); 234template void AbortFault<DataAbort>::invoke(ThreadContext *tc, 235 StaticInstPtr inst); |
234 235// return via SUBS pc, lr, xxx; rfe, movs, ldm 236 237} // namespace ArmISA | 236 237// return via SUBS pc, lr, xxx; rfe, movs, ldm 238 239} // namespace ArmISA |